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1 of 90 gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 gs1503b hd embedded audio codec data sheet www.gennum.com features ? complies with smpte 292m and smpte 299m ? single chip hd embedded audio solution ? operates as an embedded audio multiplexer or demultiplexer ? full support for 48khz synchronous 24-bit audio ? support for 8 channels of audio per device ? cascadable architecture supports up to 16 audio channels ? integrated scrambler/descrambler and word alignment ? crc error detection and insertion ? audio control packet insertion and extraction ? arbitrary data packet insertion and extraction ? 3.3v power supply with 5v tolerant i/o ?144 pin tqfp package applications hd sdi embedded audio description the gs1503b is a highly integrated, single chip solution for embedding/extracting digital audio streams into and out of high definition digital video signals. the gs1503b supports insertion/extraction of 24-bit synchronous audio data with a 48khz sample rate. audio signals with different sample rates may be converted to 48khz by using audio sample rate converters before or after the gs1503b. each gs1503b supports all processing required for embedding/extracting up to eight digital audio channels in the horizontal ancillary data space of the video chroma channel. two gs1503b?s can be cascaded for insertion/extraction of up to 16 audio channels with no external glue logic. the gs1503b supports embedding/extracting of audio control and arbitrary data packets in the horizontal ancillary data space of the video luma channel. it also supports line crc detection and insertion. the gs1503b supports hd video standards at 74.25mhz and 74.25/1.001mhz rates. it has an on chip smpte compliant scrambler/de-scrambler, and integrated word alignment. use the gs1503b with gennum?s gs1545 or gs1522 for two chip hd sdi receive or transmit solutions. the gs1503b operates from a single 3.3v power supply with 5v tolerant i/o and is packaged in a 144 pin tqfp package.
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 2 of 90 multiplex mode block diagram demultiplex mode block diagram contents features....................................................................................................................... ..........................................1 applications................................................................................................................... ......................................1 description.................................................................................................................... .......................................1 1. pin connections ............................................................................................................. ................................5 1.1 pin descriptions .......................................................................................................... ......................6 vin[19:0] 20 video detection & synchronization 20 vout[19:0] anci timing generation 4 video_det operate error crc_err de-scrambler & word alignment 20 crc inserter & scrambler trs inserter 20 dscbypass scrbypass host interface audio input interface ain1/2 ain3/4 ain5/6 ain7/8 cpuadr[8:0] cpudat[7:0] 4 9 8 2 wcina/b 3 arbitrary packet mux audio packet mux control packet mux host interface host interface 8 pkt[7:0] pkten pkteno 4 vm[3:0] mute am[1:0] 20 extf exth 2 cpucs, cpuwe, cpure vin[19:0] 20 video detection & synchronization 20 vout[19:0] delete anci anci anci timing generation 4 video_det operate error crc_err mute de-scrambler & word alignment 20 crc inserter & scrambler 20 dscbypass scrbypass host interface cpuadr[8:0] cpudat[7:0] 9 8 3 pkt[7:0] arbitrary packet demux audio output interface 4 8 aout1/2 aout3/4 aout5/6 aout7/8 2 wcouta/b pkten audio packet demux control packet demux host interface host interface 4 vm[3:0] am[1:0] 2 cpucs, cpuwe, cpure
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 3 of 90 2. electrical characteristics .................................................................................................. ....................... 10 2.1 absolute maximum ratings .................................................................................................. ..... 10 2.2 dc electrical characteristics ............................................................................................. ........ 10 2.3 ac electrical characteristics ............................................................................................. ........ 11 2.4 solder reflow profiles .................................................................................................... .............. 13 3. host interface .............................................................................................................. ................................ 14 4. detailed description........................................................................................................ .......................... 17 4.1 multiplex mode ............................................................................................................ .................. 17 4.1.1 functional overview...................................................................................................... .. 17 4.2 video standard ............................................................................................................ ................... 18 4.3 video input format ........................................................................................................ ............... 19 4.3.1 10-bit y and cb/cr input video with trs and line numbers ............................ 19 4.3.2 8-bit y and cb/cr input video with trs and line numbers.............................. 20 4.3.3 10-bit or 8-bit y and cb/cr input without trs and line numbers .................. 21 4.3.4 20-bit scrambled input ................................................................................................... .22 4.4 video output format ....................................................................................................... ............ 23 4.4.1 20-bit scrambled output................................................................................................. 2 3 4.4.2 10-bit y and cb/cr output ............................................................................................. 23 4.5 video data processing ..................................................................................................... ............ 24 4.5.1 video signal input detection......................................................................................... 24 4.5.2 video input crc error detection................................................................................. 24 4.5.3 video output crc insertion .......................................................................................... 25 4.5.4 illegal code re-mapping................................................................................................. 2 5 4.5.5 input blanking ........................................................................................................... ......... 25 4.5.6 line number insertion.................................................................................................... .26 4.5.7 trs word insertion....................................................................................................... .... 26 4.6 audio data processing ..................................................................................................... ............ 27 4.6.1 digital audio input format ............................................................................................ 27 4.6.2 digital audio input timing............................................................................................. 28 4.6.3 audio clock phase locked loop .................................................................................. 30 4.6.4 audio signal input detection ........................................................................................ 30 4.6.5 audio channel status crc error detection ............................................................. 31 4.6.6 audio input parity error detection ............................................................................. 31 4.6.7 audio channel status crc insert function.............................................................. 32 4.7 audio data packets ........................................................................................................ ............... 32 4.7.1 audio data packet structure ......................................................................................... 32 4.7.2 audio data packet did setting ..................................................................................... 33 4.7.3 audio channel multiplex enable................................................................................. 34 4.8 video switching line setting .............................................................................................. ....... 35 4.9 multiplex cascade mode .................................................................................................... ........ 36 4.10 audio control packets .................................................................................................... ........... 38 4.10.1 audio control packet structure ................................................................................. 38 4.10.2 audio control packet did setting ............................................................................. 39 4.11 arbitrary data packets ................................................................................................... ........... 41 4.11.1 arbitrary data multiplexing in external pin mode............................................. 42
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 4 of 90 4.11.2 arbitrary data multiplexing in host interface mode ......................................... 43 5. demultiplex mode ............................................................................................................ ......................... 52 5.1 functional overview ....................................................................................................... ............. 52 5.2 video standard ............................................................................................................ ................... 53 5.3 video input format ........................................................................................................ ............... 54 5.3.1 20-bit scrambled input ................................................................................................... .54 5.3.2 10-bit y and cb/cr input with trs and line numbers ......................................... 55 5.4 video output format ....................................................................................................... ............ 56 5.4.1 10-bit y and cb/cr output ............................................................................................. 56 5.4.2 20-bit scrambled output................................................................................................. 5 6 5.5 video data processing ..................................................................................................... ............ 57 5.5.1 video signal input detection......................................................................................... 57 5.5.2 video input crc error detection................................................................................. 57 5.5.3 video output crc insertion .......................................................................................... 58 5.5.4 input blanking ........................................................................................................... ......... 58 5.5.5 line number insertion.................................................................................................... .58 5.5.6 trs word insertion....................................................................................................... .... 59 5.6 audio data processing ..................................................................................................... ............ 59 5.6.1 digital audio output format......................................................................................... 59 5.6.2 digital audio output timing ......................................................................................... 60 5.6.3 audio clock phase locked loop .................................................................................. 63 5.6.4 audio data packet detection ........................................................................................ 64 5.6.5 ecc error detection & correction ............................................................................... 64 5.6.6 audio data packet error detection ............................................................................. 65 5.6.7 audio data packet did setting ..................................................................................... 66 5.7 demultiplex cascade mode .................................................................................................. ..... 67 5.8 audio control packets ..................................................................................................... ............ 68 5.8.1 audio control packet detection................................................................................... 68 5.8.2 audio control packet did setting ............................................................................... 68 5.9 arbitrary data packets .................................................................................................... ............. 70 5.9.1 arbitrary data demultiplexing in external pin mode .......................................... 71 5.9.2 arbitrary data demultiplexing in host interface mode ...................................... 71 5.10 ancillary data deletion .................................................................................................. .......... 72 5.10.1 entire ancillary data deletion ................................................................................... 72 5.10.2 audio group designation ancillary data deletion............................................. 72 5.11 demultiplex mode with word clock input ....................................................................... 73 6. using the gs1503b with the gs4911b or gs4910b ..................... ................................................... 86 7. references & bibliography ................................................................................................... ................... 87 8. packaging & ordering information ............................................................................................ .......... 88 8.1 package dimensons ......................................................................................................... ............. 88 8.2 packaging data ............................................................................................................ ................... 88 8.3 ordering information ...................................................................................................... ............. 89 9. revision history............................................................................................................ .............................. 90
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 5 of 90 1. pin connections gs1503b top view 40 39 38 37 69 60 61 62 63 64 65 66 68 59 42 41 43 44 45 46 48 49 51 52 53 54 55 56 58 70 71 72 47 50 57 67 scrbypass rsv rsv rsv rsv exth extf video_det vout0 vout1 vout6 vout7 gnd vout8 vout9 vout10 vdd vout2 gnd vout11 vout12 vout13 gnd vout14 vout15 vdd vout16 vdd vout3 vdd vout4 vout5 vout17 vout18 vout19 gnd 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 122 121 120 119 118 117 116 115 114 113 112 111 110 109 138 139 140 141 142 143 144 vin19 vdd vin18 vin17 gnd vin16 vin15 vin14 vdd vin13 vin12 vin11 gnd vin10 vin9 vin8 vdd vin7 vin6 vin5 gnd vin4 vin3 vin2 vdd vin1 vin0 cpu_sel am1 am0 vm3 vm2 vm1 vm0 reset gnd 99 100 101 102 103 104 105 107 108 98 84 85 86 87 89 91 92 94 95 96 83 73 74 75 76 77 78 79 80 81 82 88 90 93 97 106 cpudat6 vdd wcouta wcoutb aout1/2 aout3/4 aout5/6 aout7/8 gnd cpuadr8 cpuadr7 cpuadr6 vdd dec_mode gnd vclk gnd cpuadr5 cpuadr0 cpuadr2 cpuadr3 cpudat0 cpudat1 vdd cpudat2 cpuadr4 cpudat3 cpudat4 cpudat5 vdd cpucs cpudat7 cpuwe gnd cpure 9 8 7 6 5 4 3 2 10 27 26 24 25 28 23 22 21 20 19 18 17 16 15 14 13 12 11 36 35 34 33 32 31 30 29 1 vdd ain1/2 wcinb wcina dscbypass pllcntb pllcnta anci vdd gnd aclka gnd cascade mute operate crc_error pkteno pkten pkt7 vdd pkt6 pkt5 pkt4 vdd pkt3 pkt2 pkt1 pkt0 gnd error gnd aclkb mux/demux ain3/4 ain5/6 ain7/8 cpuadr1
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 6 of 90 1.1 pin descriptions table 1-1: pin descriptions number symbol typ e description 1, 14, 27, 31, 37, 52, 60, 68, 73, 84, 97, 104, 109, 117, 125, 133 vdd C +3.3v power supply pins. 2 ain7/8 i audio signal input for channels 7 and 8. aes/ebu digital audio data is bi-phase mark encoded. for all non-aes/ebu input modes, bi-phase mark encoding is not required. 3 ain5/6 i audio signal input for channels 5 and 6. aes/ebu digital audio data is bi-phase mark encoded. for all non-aes/ebu input modes, bi-phase mark encoding is not required. 4 ain3/4 i audio signal input for channels 3 and 4. aes/ebu digital audio data is bi-phase mark encoded. for all non-aes/ebu input modes, bi-phase mark encoding is not required. 5 ain1/2 i audio signal input for channels 1 and 2. aes/ebu digital audio data is bi-phase mark encoded. for all non-aes/ebu input modes, bi-phase mark encoding is not required. 6 wcinb i 48khz word clock for channels 5 to 8. used only when operating in multiplex mode and when the audio source is not an aes/ebu data stream. this pin should be grounded when inputting aes/ebu digital audio data or when operating in demultiplex mode (dec_mode set low). 7 wcina i 48khz word clock for channels 1 to 4. used only when operating in multiplex mode and when the audio source is not an aes/ebu data stream. this pin should be grounded when inputting aes/ebu digital audio data or when operating in demultiplex mode (dec_mode set low). 8 dscbypass i descrambler bypass. when set low, the internal smpte 292m descrambler is enabled. when set high, the internal smpte 292m descrambler is bypassed. the video input to the device must be word aligned. 9 pllcntb o audio clock pll control signal for channels 5 to 8. 10 pllcnta o audio clock pll control signal for channels 1 to 4. 11 cascade i cascade mode select. when set high, the gs1503b will default to audio groups 3 and 4. two gs1503b devices can then be cascaded in series to allow up to 16 channels of audio to be multiplexed or demultiplexed (only one device requires cascade to be set high). when set low, the gs1503b will default to audio groups 1 and 2. 12 mute i audio mute. in multiplex mode, when set high, the embedded audio packets are forced to '0'. in demultiplex mode, when set high, the audio output data is forced to "0". 13 anci i ancillary data delete select. valid in demultiplex mode only. when set high, all ancillary data packets are removed from both the luma and chroma channels of the input video signal. the data contained in the packets are output at the corresponding pins. when set low, all ancillary data packets remain in the video signal. see demultiplex mode with word clock input on page 73 . 15 mux /demux i mode of operation. when set low, the gs1503b operates in multiplex mode. when set high, the gs1503b operates in demultiplex mode.
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 7 of 90 16, 18, 20, 36, 48, 56, 64, 72, 80, 86, 88, 108, 113, 121, 129, 144 gnd C device ground. 17 aclka i input audio signal clock at 6.144 mhz (128 fs) for channels 1 to 4. 19 aclkb i input audio signal clock at 6.144 mhz (128 fs) for channels 5 to 8. 21 error o format error indicator. when high, the incoming video data stream contains trs errors or there are errors within the incoming ancillary data packets. 22 operate o audio processing indicator. when high, audio data is being multiplexed or demultiplexed. 23 crc_error o crc error indicator. will be set high when a crc error is detected in the incoming video data stream. 24 pkteno o arbitrary data packet timing signal. valid in multiplex mode only. will be high when arbitrary data packets can be input to the device. this signal is only valid when multiplexing arbitrary data packets via the pkt[7:0] bus. see figure 4-22 for timing. 25 pkten i/o arbitrary data packet enable. in multiplex mode, pkten is an input and must be set high two vclk cycles after the pkteno signal goes high. arbitrary packet data is input to the device two vclk cycles after pkten is set high. in demultiplex mode, pkten is an output and is set high two vclk cycles before the device outputs arbitrary packet data. see figure 4-22 and figure 5-12 . 26, 28, 29, 30, 32, 33, 34, 35 pkt[7:0] i/o arbitrary data i/o bus. pkt[7] is the ms b and pkt[0] is the lsb. in multiplex mode, the user must input the arbitrary data packet words starting from the data identification (did) to the last user data word (udw) according to smpte 291m. the gs1503b internally converts the data to 10 bits by generating the parity bit (bit 8) and inversion bit (bit 9). the checksum (cs) word is also generated internally. in demultiplex mode, the gs9023 outputs the arbitrary data packet words starting from the did to the last udw. see figure 4-22 and figure 5-12 . 38 scrbypass i scrambler bypass. when set low, the output video stream is scrambled according to smpte 292m and nrz(i) encoded. when set high, the scrambler and nrz(i) encoder are bypassed. 39, 40, 41, 42 rsv C connect to ground. 43 exth i/o horizontal sync signal. the gs1503b outputs a horizontal sync signal derived from the incoming trs. in multiplex mode, with ext_sel set high in the host interface, a horizontal sync signal can be input to the device for trs and line number insertion. 44 extf i/o field sync signal. the gs1503b outputs a field sync signal derived from the incoming trs. in multiplex mode, with ext_sel set hi gh in the host interface, a field sync signal can be input to the device for trs and line number insertion. for progressive formats, a signal with a high to low transition at the position of line one must be provided. see figure 4-6 and figure 4-7 . 45 video_det o video input signal detection. indicates that the device has detected a valid video input stream. note: when ext_sel is set high in the host interface, video_det will indicate when valid exth and extf signals have been detected. table 1-1: pin descriptions (continued) number symbol typ e description
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 8 of 90 71, 70, 69, 67, 66, 65, 63, 62, 61, 59, 58, 57, 55, 54, 53, 51, 50, 49, 47, 46 vout[19:0] o parallel digital video signal output. vout[19] is the msb and vout[0] is the lsb. 74 wcouta o 48khz word clock for channels 1 to 4. valid only when operating in demultiplex mode. 75 wcoutb o 48khz word clock for channels 5 to 8. valid only when operating in demultiplex mode. 76 aout1/2 o audio signal output for channels 1 and 2. the aes/ebu digital audio output is bi-phase mark encoded. in both non-aes/ebu modes, the output is not bi-phase mark encoded. 77 aout3/4 o audio signal output for channels 3 and 4. the aes/ebu digital audio output is bi-phase mark encoded. in both non-aes/ebu modes, the output is not bi-phase mark encoded. 78 aout5/6 o audio signal output for channels 5 and 6. the aes/ebu digital audio output is bi-phase mark encoded. in both non-aes/ebu modes, the output is not bi-phase mark encoded. 79 aout7/8 o audio signal output for channels 7 and 8. the aes/ebu digital audio output is bi-phase mark encoded. in both non-aes/ebu modes, the output is not bi-phase mark encoded. 85 dec_mode i demultiplex mode select. valid in demultiplex mode only. when set high, the gs1503b requires a 48khz word clock input at wcina and wcinb. this word clock must be synchronous to the word clock used to embed the audio data. the embedded audio clock phase information in the ancillary data packet will be ignored. see demultiplex mode with word clock input on page 73 . 87 vclk i video clock signal input. 81, 82, 83, 89, 94, 93, 92, 91, 90 cpuadr[8:0] i host interface address bus. cpuadr[8] is the msb a nd cpuadr[0] is the lsb. in host interface mode b (cpu_sel set low), cp uadr[1:0] are used as the host interface control bus. see table 3-4 . 103, 102, 101, 100, 99, 98, 96, 95 cpudat[7:0] i/o host interface data bus. cpudat[7] is the msb and cpudat[0] is the lsb. in host interface mode b (cpu_sel set low), cpudat[7:0] are used as the host interface address and data bus. 105 cpucs i chip select for host interface. active low. 106 cpure i read enable for host interface. active low. in host interface mode b (cpu_sel set low), this input is not used. 107 cpuwe i write enable for host interface. active low. in host interface mode b (cpu_sel set low), this input is used as the host interface control enable. 110, 111, 112, 114, 115, 116, 118, 119, 120, 122, 123, 124, 126, 127, 128, 130, 131, 132, 134, 135 vin[19:0] i parallel digital video signal input. vin[19] is the msb and vin[0] is the lsb. table 1-1: pin descriptions (continued) number symbol typ e description
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 9 of 90 136 cpu_sel i host interface mode select. when set high, the gs1503b is configured for host interface mode a. when set low, the gs1503b is configured for host interface mode b. 137, 138 am[1:0] i audio format select. in multiplex mode, am[1:0] indicates the input audio data format. in demultiplex mode, am[1:0] indicates the output audio data format. am[1] is the msb and am[0] is the lsb. see table 4-16 and table 5-13 . 139, 140, 141, 142 vm[3:0] i video standard select. vm[3] is the msb and vm[0] is the lsb. see table 4-1 or table 5-1 . 143 reset i device reset. active low. table 1-1: pin descriptions (continued) number symbol typ e description
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 10 of 90 2. electrical characteristics 2.1 absolute maximum ratings 2.2 dc electrical characteristics table 2-1: absolute maximum ratings parameter value supply voltage -0.3v to 4.0v input voltage (any input) -0.3 to 5.5v operating temperature 0c to 70c storage temperature -65c to 150c lead temperature (soldering, 10 sec.) 260c table 2-2: dc electrical characteristics t a = 0c to 70c unless otherwise shown. parameter symbol conditions min ty p max units supply voltage v dd 3.3v operating range 3.0 3.3 3.6 v supply current i dd v dd = 3.3v 270 ma input current i in C-1C1 a hi-z output leakage current i oz C-1C1a output voltage, logic high v oh i oh = -12ma v dd -0.4 C C v output voltage, logic low v ol i ol = 12ma C C 0.4 v input voltage, logic high v ih ttl level 2.0 C C v input voltage, logic low v il ttl level C C 0.8 v input capacitance c i f = 1mhz, v dd = 0v C C 10 pf output capacitance c o f = 1mhz, v dd = 0v C C 10 pf i/o capacitance c io f = 1mhz, v dd = 0v C C 10 pf
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 11 of 90 2.3 ac electrical characteristics figure 2-1: video data input setup & hold time table 2-3: ac electrical characteristics v dd = 3.3v 5%, t a = 0c to 70c unless otherwise shown. parameter symbol conditions min ty p max units video clock frequency C C 74.25 80 mhz video clock pulse width low t vpwl C5.0CCns video clock pulse width high t vpwh C5.0CCns video input data setup time t vs C3.5CCns video input data hold time t vh C1.0CCns video output data delay time t vod with 10pf loading C C 8.5 ns video output data hold time t voh with 10pf loading 1.0 C C ns audio clock frequency C C 6.144 C mhz audio clock pulse width low t apwl C60CCns audio clock pulse width high t apwh C60CCns audio input data setup time t as C10.5CCns audio input data hold time t ah C1.0CCns audio output data delay time t aod with 10pf loading C C 20.0 ns audio output data hold time t aoh with 10pf loading 1.0 C C ns reset pulse width t reset C1CCms device latency C multiplexer mode demultiplexer mode 53 53 53 53 53 53 pclks vclk data* * vin[19:0], extf, exth, pkten, pkt[7:0] t vs t vh
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 12 of 90 figure 2-2: video data output delay & hold time figure 2-3: audio data input setup & hold time figure 2-4: audio data output delay & hold time figure 2-5: reset timing vclk data* * vout[19:0], extf, exth, pkten, pkt[7:0] t voh t vod aclka/b data* * wcina, ain1/2, ain3/4, wcinb, ain5/6, ain7/8 t as t ah aclka/b data* * aout1/2, aout3/4, aout5/6, aout7/8 t aoh t aod vdd reset t reset vdd(min) t reset
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 13 of 90 2.4 solder reflow profiles figure 2-6: maximum pb-free solder reflow profile (preferred) figure 2-7: standard eutectic solder reflow profile 25?c 100?c 150?c 183?c 230?c 220?c time temperature 6 min. max 120 sec. max 60-150 sec. 10-20 sec. 3?c/sec max 6?c/sec max 25?c 150?c 200?c 217?c 260?c 250?c time temperature 8 min. max 60-180 sec. max 60-150 sec. 20-40 sec. 3?c/sec max 6?c/sec max
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 14 of 90 3. host interface figure 3-1: host interface mode a timing (cpu_sel set high) table 3-1: mode a (cpu_sel set high) parameter number min typ max units read cycle time 1 50 C C ns read chip select setup time 2 0 C C ns read address setup time 3 15 C C ns read data output delay time 4 C C 15 ns read data hold time 5 0 C C ns write cycle time 6 50 C C ns write chip select setup time 7 10 C C ns write address setup time 8 10 C C ns write data setup time 9 10 C C ns write data hold time 10 0 C C ns cpuadr[8:0] cpudat[7:0] cpucs cpure valid data valid data 1 3 45 cpuwe address address 2 6 7 8 910 read cycle write cycle
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 15 of 90 figure 3-2: host interface mode b read cycle timing (cpu_sel set low) table 3-2: mode b read cycle (cpu_sel set low) parameter number min typ max units read address cycle time 1 80 C C ns read cycle time 2 80 C C ns read enable setup time 3 20 C C ns read address setup time 4 20 C C ns read chip select setup time 5 10 C C ns read chip select hold time 6 0 C C ns read data output delay time 7 C C 10 ns read data hold time 8 0 C C ns table 3-3: mode b write cycle (cpu_sel set low) parameter number min typ max units write address cycle time 1 80 C C ns write cycle time 2 80 C C ns write enable setup time 3 20 C C ns write address setup time 4 20 C C ns write chip select setup time 5 10 C C ns write chip select hold time 6 0 C C ns write data setup time 7 30 C C ns write data hold time 8 0 C C ns cpuadr[1:0] cpudat[7:0] cpucs cpuwe 01 00 11 upper address lower address read data 112 3 4 5 3 4 5 666 3 5 7 8
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 16 of 90 figure 3-3: host interface mode b write cycle timing (cpu_sel set low) table 3-4: host interface mode b control codes cpuadr[1:0] data bus operation 01 upper address 00 lower address 11 read data 10 write data cpuadr[1:0] cpudat[7:0] cpucs cpuwe 01 00 10 upper address lower address write data 112 3 4 5 3 4 5 666 3 5 7 8
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 17 of 90 4. detailed description 4.1 multiplex mode 4.1.1 functional overview the gs1503b hd embedded audio codec fully supports the multiplexing of audio data packets, audio control packets and ar bitrary data packets as per smpte 291m and 299m. the device can be configured to operate with all video standards defined in smpte 292m, levels a through m. the gs1503b also supports the 1080/24psf, 25psf and 30psf video formats as described in smpte rp211. the video input format can be one of the following configurations: ?10-bit y and c b /c r input with trs and line numbers ?8-bit y and c b /c r input with trs and line numbers 10-bit or 8-bit y and c b /c r input without trs and line numbers (gs1503b will insert trs and line numbers based on extf and exth inputs) ?20-bit scrambled input the video output format can be one of the following configurations: ?20-bit scrambled output ?10-bit y and c b /c r output up to a maximum of 8 channels of 48khz digital audio can be multiplexed per device. the audio input format can be selected as either aes/ebu, or one of two serial audio data input modes. a maximum of 16 channels of audio can be multiplexed by serially cascading two devices. audio control packets, as defined in smpte 299m, can also be multiplexed to provide information to receivers about the nature of the embedded audio data. the contents of the audio control packet can be programmed via the host interface. the gs1503b will also multiplex arbitrary data packets as defined in smpte 291m. the arbitrary data packets can serve as an auxiliary data signal for proprietary applications. the gs1503b can be configured to multiplex arbitrary data packets, input via the host interface or using dedicated external pins. up to a maximum of 255 8-bit words can be multiplexed (excluding ancilla ry data flags and checksum). to use the gs1503b in multiplex mode, set the mux /demux external pin low.
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 18 of 90 4.2 video standard the video standard is selected from the vm[3:0] external pins or vm[3:0] bits 3-0 in host interface register 000h. to configure the video standard via the host interface, vm_sel bit 7 in host interface register 000h must be set high. the gs1503b will default to the vm[3:0] external pin setting. the supported video standards are listed in table 4-1 . table 4-1: supported video standards vm [3:0] input format reference smpte document smpte 292m level 1110b 1035i (30 & 30/1.001 hz) 260m a, b 1100b 1080i (25 hz) 295m c 1000b 1080i/1080sf (30 & 30/1.001 hz) 274m, rp211 d, e 1010b 1080i/1080sf (25 hz) 274m, rp211 f 1111b 1080sf (24 & 24/1.001 hz) rp211 0010b 1080p (30 & 30/1.001 hz) 274m g, h 0100b 1080p (25 hz) 274m i 0110b 1080p (24 & 24/1.001 hz) 274m j, k 0000b 720p (60 & 60/1.001 hz) 296m l, m 0001b 720p (30 & 30/1.001 hz) 296m 0011b 720p (50 hz) 296m 0101b 720p (25 hz) 296m 0111b 720p (24 & 24/1.001 hz) 296m all other settings are reserved table 4-2: register settings name description address bit setting default vm_sel 0: external pin select 1: register select 000 7 1 0 vm[3:0] video formal selection (vm[3] is msb) 000 3-0 see table 4-1 0
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 19 of 90 4.3 video input format 4.3.1 10-bit y and c b /c r input video with trs and line numbers figure 4-1: configuration for 10-bit y and c b /c r input video with trs and line numbers figure 4-2: video input format 10-bit with trs and line numbers y[9:0] c b /c r [9:0] vin[19:10] vin[9:0] dscbypass extf exth gs1503b +3.3v vn y, c b /c r 3ff 3ff xyz 000 000 000 000 xyz 10-bit ln1 ln0 crc0 crc1 v0 video eav sav 0 3 8 table 4-3: register settings name description address bit setting default ext_sel 0: exth/extf output select 1: exth/extf input select 001 3 0 0 8bit_sel 0: 10-bit mode select 1: 8-bit mode select 001 10 0 dscbypass 0: descrambling enabled 1: bypass descrambling 001 01 0
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 20 of 90 4.3.2 8-bit y and c b /c r input video with trs and line numbers figure 4-3: configuration for 8-bit y and c b /c r input video with trs and line numbers figure 4-4: video input format 8-bit with trs and line numbers y[9:0] c b /c r [9:0] vin[19:12] vin[9:2] dscbypass extf exth gs1503b vin[1:0] vin[11:10] +3.3v vn y, c b /c r ff ff xy 00 00 00 00 xy 8-bit ln1 ln0 v0 video eav sav 0 3 8 table 4-4: register settings name description address bit setting default ext_sel 0: exth/extf output select 1: exth/extf input select 001 3 0 0 8bit_sel 0: 10-bit mode select 1: 8-bit mode select 001 11 0 dscbypass 0: descrambling enabled 1: bypass descrambling 001 01 0
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 21 of 90 4.3.3 10-bit or 8-bit y and c b /c r input without trs and line numbers the gs1503b will insert trs and line numbers based on extf and exth inputs. see figure 4-6 for timing. in progressive format video standards, a high-to-low edge signal must be input at the extf external pin on every frame to indicate the position of line 1. see figure 4-7 . figure 4-5: configuration for 10-bit or 8-bit y and c b /c r input video without trs and line numbers figure 4-6: video input format (8/10-bit without trs and line numbers) figure 4-7: 15 video input format (progressive) y[9:0] c b /c r [9:0] vin[19:10] vin[9:0] dscbypass extf exth gs1503b +3.3v vn y, c b /c r 8/10-bit v0 video 0 3 8 4 vclk exth extf vn y, c b /c r 8/10-bit v0 video 0 3 8 4 vclk exth extf line 1
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 22 of 90 4.3.4 20-bit scrambled input figure 4-8: configuration for 20-bit scrambled input table 4-5: register settings name description address bit setting default ext_sel 0: exth/extf output select 1: exth/extf input select 001 3 1 0 8bit_sel 0: 10-bit mode select 1: 8-bit mode select 001 10 or 1 0 dscbypass 0: descrambling enabled 1: bypass descrambling 001 01 0 y/c b /c r [19:0] vin[19:0] dscbypass gs1503b table 4-6: register settings (default mode) name description address bit setting default ext_sel 0: exth/extf output select 1: exth/extf input select 001 3 0 0 8bit_sel 0: 10-bit mode select 1: 8-bit mode select 001 10 0 dscbypass 0: descrambling enabled 1: bypass descrambling 001 00 0
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 23 of 90 4.4 video output format 4.4.1 20-bit scrambled output figure 4-9: configuration for 20-bit scrambled output 4.4.2 10-bit y and c b /c r output figure 4-10: configuration for 10-bit y and c b /c r output y/c b /c r [19:0] vout[19:0] scrbypass gs1503b table 4-7: register settings (default mode) name description address bit setting default scrbypass 0: smpte 292m scrambling enabled 1: bypass smpte 292m scrambling 001 2 0 0 y[9:0] c b /c r [9:0] vout[19:10] vout[9:0] scrbypass gs1503b +3.3v
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 24 of 90 4.5 video data processing 4.5.1 video signal input detection the gs1503b will set the video_det external pin high when three consecutive trs are detected in the input video signal. also, the video_det bit of host interface register 000h is set high. 4.5.2 video input crc error detection the gs1503b will set the crc_err external pin high when a crc error is detected in the input video signal. also, the crc_err bit 5 of host interface register 000h is set high. the number of crc errors accumulated in one video frame can be read form crc_cnt[11:0] in host interface registers 006h and 007h. table 4-8: register settings name description address bit setting default scrbypass 0: smpte 292m scrambling enabled 1: bypass smpte 292m scrambling 001 2 1 0 table 4-9: register settings name description address bit setting default video_det video input signal detection (1: detection) 000 6 C 0 table 4-10: register settings name description address bit setting default crc_err video input signal crc error detection (1: detection) 000 5 C 0 crc_cnt[11:0] video input signal crc error accumulation in 1 video frame 006 007 3-0 7-0 C0
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 25 of 90 4.5.3 video output crc insertion when the crc_ins bit 4 of host interface register 000h is set high, the gs1503b will re-calculate the video line crc words. the re-calculated crc words are inserted in the video output signal. when crc_ins is set low, the line crc words are not updated and existing crc words at the input of the device will be output unchanged. 4.5.4 illegal code re-mapping when limit_on bit 4 of host interface register 008h is set high, input video words between 000-003 are re-mapped to 004, and values between 3fc-3ff are re-mapped to 3fb. valid only when the ext_sel bit 3 of host interface register 000h is set high. 4.5.5 input blanking when vblk_ins bit 3 of host interface register 008h is set high, the input video vertical blanking will be set to 040h for the luma channel and 200h for the chroma channel. when hblk_ins bit 2 of host interface register 008h is set high, the input video horizontal blanking will be set to 040h for the luma channel and 200h for the chroma channel. the trs, line number and crc words will also be set to blanking values. the blanking function is performed at the output of the gs1503b video data stream. if the hblk_ins bit is set high, any multiplexed audio will be replaced with blanking codes. table 4-11: register settings name description address bit setting default crc_ins video line crc insertion (1: insertion) 000 4 1 1 table 4-12: register settings name description address bit setting default ext_sel 0: exth/extf output select 1: exth/extf input select 001 3 1 0 limit_on illegal code re-mapping (1: enabled) 008 4 1 0 table 4-13: register settings name description address bit setting default vblk_ins input vertical blanking (1: enabled) 008 3 1 0 hblk_ins input horizontal blanking (1: enabled) 008 210
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 26 of 90 4.5.6 line number insertion when ln_ins bit 1 of host interface register 008h is set high, the gs1503b will insert line numbers into the video data stream. when set low, existing line numbers will remain in the output video stream. when ext_sel bit 3 of host interface register 001h is set high, line numbers will be inserted based on the timing of exth and extf input signals. 4.5.7 trs word insertion when trs_ins bit 0 of host interface register 008h is set high, the gs1503b will insert trs codes into the video data stream. when set low, existing trs codes will remain in the output video stream. when ext_sel bit 3 of host interface register 001h is set high, trs codes will be inserted based on the timing of exth and extf input signals. table 4-14: register settings name description address bit setting default ln_ins line number insertion (1: enabled) 008 1 1 1 table 4-15: register settings name description address bit setting default trs_ins trs word insertion (1: enabled) 008 0 1 1
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 27 of 90 4.6 audio data processing 4.6.1 digital audio input format the gs1503b will accept two audio input formats, aes/ebu digital audio input and serial input, as listed in table 4-16 . serial input can be formatted in the following two modes. see figure 4-11 . ? 24-bit left justified; msb first ? 24-bit right justified; msb last the audio input format is configured using the am[1:0] external pins or via am[1:0] bits 1-0 in host interface register 010h. to configure the audio input format via the host interface, am_sel bit 7 in host interface register 010h must be set high. the gs1503b will default to the am[1:0] external pin setting. figure 4-11: audio input formats table 4-16: audio input formats am[1:0] audio input format 0 serial audio input: 24-bit left justified; msb first 1 serial audio input: 24-bit right justified; msb last 2 aes/ebu audio input table 4-17: register settings name description address bit setting default am_sel 0: external pin setting 1: register setting 010 7 1 0 am[1:0] audio input format selection (am[1] is msb) 010 1-0 see table 4-11 0 23 channel 1 msb channel 2 wcina/wcinb 0 0 lsb 23 23 msb 0 0 lsb 23 mode1 mode0 mode2 (aes/ebu) sync preamble 24-bit audio sample word vucp 0 3 4 2728293031 channel status bit validity bit user data bit parity bit sync preamble 24-bit audio sample word vucp 0 3 4 2728293031
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 28 of 90 4.6.2 digital audio input timing 4.6.2.1 aes/ebu format input a 6.144mhz (128fs) audio clock must be supplied to the aclka and aclkb inputs. aclka is used to clock the aes/ebu digital audio signal for channels 1 to 4 (ain1/2 and ain3/4) into the device. aclkb is used to clock the aes/ebu digital audio signal for channels 5 to 8 (ain5/6 and ain7/8) into the device. in aes/ebu input mode, the wcinb and wcinb external pins should be grounded. see figure 4-12 for timing. figure 4-12: aes/ebu input configuration and timing aclka/b ain1/2, ain3/4 ain5/6, ain7/8 6.144mhz y/c b /c r [19:0] vin[19:0] ain5/6 gs1503b ain1/2 ain3/4 ain7/8 aclka aclkb audio channels 1 & 2 audio channels 3 & 4 audio channels 5 & 6 audio channels 7 & 8 6.144mhz (128 fs) 6.144mhz (128 fs) wcina wcinb
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 29 of 90 4.6.2.2 serial audio input modes a 6.144mhz (128fs) audio clock must be supplied to the aclka and aclkb inputs. the gs1503b divides this clock by 2 to clock the 3.072mhz audio data. an audio word clock at 48khz (fs) must also be supplied to the wcina and wcinb inputs, as shown in figure 4-13 . the audio_cs[183:0] bits in host interface registers 058h to 06eh can be used to enter the 23 8-bit bytes of the audio channel status block, as defined in aes3-1992. note: the crc byte is generated internally by the gs1503b. the gs1503b will default to professional audio mode with 24-bit word length and emphasis off. see table 4-34 . figure 4-13: serial audio input configuration and timing y/c b /c r [19:0] vin[19:0] ain5/6 gs1503b ain1/2 ain3/4 ain7/8 aclka aclkb audio channels 1 & 2 audio channels 3 & 4 audio channels 5 & 6 audio channels 7 & 8 6.144mhz (128 fs) 6.144mhz (128 fs) aclka/b ain1/2, ain3/4 ain5/6, ain7/8 64 clks 48khz (fs) 48khz (fs) wcina wcinb wcina/b 64 clks
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 30 of 90 4.6.3 audio clock phase locked loop figure 4-14 shows the configuration for deriving the 6.144mhz audio clock in aes/ebu audio input mode. the gs1503b will internally synchronize the aes/ebu audio input to the corresponding aclk, using the clock extracted from the aes/ebu bi-phase mark encoding. this configuration is not required for serial audio input modes. figure 4-14: block diagram of gs1503b audio clock pll 4.6.4 audio signal input detection the audio input signal detect registers will be set high in aes/ebu audio mode when the preamble of the audio input data is detected 3 times consecutively. in serial audio input mode, the gs1503b will set the audio input signal detect registers high when a 48khz word clock is detected at the corresponding inputs. audio channels 1 to 4 will be set when wcina is validated, and audio channels 5 to 8 when wcinb is validated. host interface register 010h, bits 6-3, report the individual audio channels pairs detected. y/c b /c r [19:0] vin[19:0] ain5/6 gs1503b ain1/2 ain3/4 ain7/8 aclka aclkb audio channels 1 & 2 audio channels 3 & 4 audio channels 5 & 6 audio channels 7 & 8 6.144mhz (128 fs) pllcnta pllcntb low pass filter vcxo 24.576mhz vcxo 24.576mhz 4 4 6.144mhz (128 fs) low pass filter table 4-18: register settings name description address bit setting default aud7/8_det ch7/8 audio input signal detection (1:detection) 010 6 C 0 aud5/6_det ch5/6 audio input signal detection (1:detection) 010 5C 0
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 31 of 90 4.6.5 audio channel status crc error detection in aes/ebu audio mode, the gs1503b will check the channel status crc for errors. if any channel status crc errors are detected in an aes/ebu audio input channel pair, the corresponding bit in host interface register 011h will be set high. in serial audio input mode, the crc error flags are always set low. 4.6.6 audio input parity error detection in aes/ebu audio mode, the gs1503b will check for audio parity errors. if any audio parity errors are detected in an aes/ebu audio input channel pair, the corresponding bit in host interface register 012h will be set high. in serial audio input mode, the audio parity error flags are always set low. aud3/4_det ch3/4 audio input signal detection (1:detection) 010 4C 0 aud1/2_det ch1/2 audio input signal detection (1:detection) 010 3C 0 table 4-18: register settings name description address bit setting default table 4-19: register settings name description address bit setting default acrc7/8_err ch7/8 audio channel status crc error detection (1: detection) 011 3 C 0 acrc5/6_err ch5/6 audio channel status crc error detection (1: detection) 011 2C 0 acrc3/4_err ch3/4 audio channel status crc error detection (1: detection) 011 1C 0 acrc1/2_err ch1/2 audio channel status crc error detection (1: detection) 011 0C 0 table 4-20: register settings name description address bit setting default ap7/8_err ch7/8 audio parity error detection (1: detection) 012 3 C 0 ap5/6_err ch5/6 audio parity error detection (1: detection) 012 2C 0 ap3/4_err ch3/4 audio parity error detection (1: detection) 012 1C 0 ap1/2_err ch1/2 audio parity error detection (1: detection) 012 0C 0
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 32 of 90 4.6.7 audio channel status crc insert function when bits 7-4 of host interface register 011h are set high, the gs1503b will re-calculate the channel status crc word for the corresponding audio input channel pair. the re-calculated channel status crc word is multiplexed into the audio data packet as per smpte 299m. when bits 3-0 of host interface register 011h are set low, the channel status crc word is not updated and the existing channel status crc word will be multiplexed. in serial audio input mode, these registers should be set low. 4.7 audio data packets 4.7.1 audio data packet structure figure 4-15 shows the structure of the audio data packets as defined in smpte 299m. the audio data packets are multiplexed into the chroma channel of the video data stream. table 4-22 lists the description of the individual audio data packet words. note that the gs1503b will automatically generate certain audio data packet words. figure 4-15: audio data packet structure table 4-21: register settings name description address bit setting default acrc7/8_ins ch7/8 audio channel status crc insertion (1: insertion) 011 7 1 0 acrc5/6_ins ch5/6 audio channel status crc insertion (1: insertion) 011 61 0 acrc3/4_ins ch3/4 audio channel status crc insertion (1: insertion) 011 51 0 acrc1/2_ins ch1/2 audio channel status crc insertion (1: insertion) 011 41 0 adf user data words ecc0 10-bit did dbn dc clk ch1 ch2 ch3 ch4 ecc1 ecc2 ecc3 ecc4 ecc5 cs ecc protected
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 33 of 90 4.7.2 audio data packet did setting the audio group did for audio input channels 1 to 4 (ain1/2 and ain3/4) is set in dataida[1:0] bits 1-0 of host interface register 014h. the audio group did for audio input channels 5 to 8 (ain5/6 and ain7/8) is set in dataidb[1:0] bits 3-2 of host interface register 014h. table 4-23 shows the 2-bit host interface setting for the corresponding audio group did. when cascade is set low (external pin or register), the gs1503b will default to audio groups 1 and 2, where ain1/2 and ain3/4 will be multiplexed with audio group 1 did, and ain5/6 and ain7/8 with audio group 2 did. table 4-22: audio data packet word descriptions name no of words description data auto-generation adf 3 ancillary data flag 000h 3ffh 3ffh yes did 1 audio group data id 2e7h 1e6h 1e5h 2e4h see table 4-23 in section 4.7.2 dbn 1 data block number repeat 1-255 yes dc 1 data count 218h yes clk 2 audio clock phase data C yes ch1 4 channel 1 audio data C ch2 4 channel 2 audio data C ch3 4 channel 3 audio data C ch4 4 channel 4 audio data C ecc0-5 6 error correction code for lower 8 bits of first 24 words Cyes cs 1 checksum. calculates the sum of lower 9 bits of 22 words from did Cyes table 4-23: audio data packet group did host interface setting audio group 10-bit data host interface register setting (2-bit) 1 2e7h 11b 2 1e6h 10b 3 1e5h 01b 4 2e4h 00b
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 34 of 90 when cascade is set high (external pin or register), the gs1503b will default to audio groups 3 and 4, where ain1/2 and ain3/4 will be multiplexed with audio group 3 did, and ain5/6 and ain7/8 with audio group 4 did. 4.7.3 audio channel multiplex enable multiplexing of individual audio channels is enabled using the chact[7:0] bits 7-0 of host interface register 013h. when set high, the corresponding audio channel is multiplexed into the audio data packet in the chroma video data stream. chact7 corresponds to audio input channel 8 and chact0 corresponds to audio input channel 1. when all bits are set low, no audio data packets will be multiplexed and the gs1503b will be in bypass mode. table 4-24: register settings (cascade set low) name description address bit setting default dataida [1-0] ch1-4 audio data packet did setting 014 1-0 see table 4-23 11b dataidb [1-0] ch5-8 audio data packet did setting 014 3-2 10b table 4-25: register settings (cascade set high) name description address bit setting default dataida [1-0] ch1-4 audio data packet did setting 014 1-0 see table 4-23 01b dataidb [1-0] ch5-8 audio data packet did setting 014 3-2 00b table 4-26: register settings name description address bit setting default chact7 ch8 multiplex enable (1: enabled) 013 7 C 1 chact6 ch7 multiplex enable (1: enabled) 013 6 ? 1 chact5 ch6 multiplex enable (1: enabled) 013 5 ? 1 chact4 ch5 multiplex enable (1: enabled) 013 4 ? 1 chact3 ch4 multiplex enable (1: enabled) 013 3 ? 1 chact2 ch3 multiplex enable (1: enabled) 013 2 ? 1 chact1 ch2 multiplex enable (1: enabled) 013 1 ? 1 chact0 ch1 multiplex enable (1: enabled) 013 0 ? 1
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 35 of 90 4.8 video switching line setting the video switching point for field 1 and field 2 can be configured via the gs1503b host interface. the sw_lna[12:0] register is used to configure the video switching line for field 1, and sw_lnb[12:0] to set video switching line for field 2. in progressive format video standards, only the sw_lna[12:0] register is used. the default settings are line 7 for field 1 and line 569 for fiel d 2 as defined in smpte 299m. the gs1503b will not multiplex any audio data packets in the line immediately after the video switching point. for example, with the default setting of line 7 field 1, there will be no audio data packets in line 8. the next packets will appear on line 9. audio control packets will be multiplexed once per field, two lines after the video switching point (on line 9, using the previous example). arbitrary data packets will not be multiplexed in the two lines following the video switching point . note: the smpte 299m standard defines the video switching point as lines 7 and 569. if the sw_lna[12:0] and sw_lnb[12:0] registers are programmed with values other than lines 7 and 569, the output of the gs1503b is not guaranteed to be compatible with all hd audio demultiplex systems. with non-smpte 299m compliant switch line settings, the user should avoid inputting a video data stream to the gs1503b, which already contains embedded audio data and control packets. for reliable operation, non-smpte 299m compliant video data streams with embedded audio should not be used in conjunction with the gs1503b in multiplex mode. table 4-27: register settings name description address bit setting default sw_lna[12:0] video field 1 switching point setting 004 005 4-0 7-0 C7d sw_lnb[12:0] video field 2 switching point setting 002 003 4-0 7-0 C 569d
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 36 of 90 4.9 multiplex cascade mode two gs1503b devices can be cascaded in series to allow up to 16 channels of audio to be multiplexed (only one device requires cascade to be set high). figure 4-16 shows the cascade architecture for a 16-channel system. to configure the gs1503b for cascade mode, the cascade external pin or cascade bit 7 of host interface register 014h is set high. when set high, the gs1503b will default to audio groups 3 and 4. when set low, the gs1503b will default to audio groups 1 and 2. figure 4-16: multiplexing 16 channels of audio using cascade architecture when cascade is set low, the gs1503b will multiplex audio data and control packets as shown in figure 4-17 (note: only the chroma channel of the video data stream is shown). any existing audio data or control packets will be deleted and replaced with blanking data before the new packets are multiplexed. new packets are multiplexed immediately after the two video line crc words. when cascade is set high, the gs1503b will multiplex the audio data and control packets immediately after the existing packets, as shown in figure 4-18 . avoid multiplexing new ancillary data packets with the same audio group did as existing packets. y/c b /c r [19:0] vin[19:0] ain5/6 gs1503b ain7/8 audio channels 1 & 2 audio channels 3 & 4 audio channels 5 & 6 audio channels 7 & 8 cascade vout[19:0] audio group 1 audio group 2 ain1/2 ain3/4 y/c b /c r [19:0] vin[19:0] ain5/6 gs1503b ain7/8 audio channels 9 & 10 audio channels 11 & 12 audio channels 13 & 14 audio channels 15 & 16 cascade vout[19:0] audio group 3 audio group 4 ain1/2 ain3/4 y/c b /c r [19:0] +3.3v table 4-28: register settings name description address bit setting default cascade cascade enable (1: enabled) 014 7 1 0
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 37 of 90 figure 4-17: insertion of audio groups 1 & 2, without / with existing packets) figure 4-18: insertion of audio groups 3 & 4 in cascade mode the gs1503b assumes that the ancillary data space from the first blanking location to the sav contains no ancillary data packets. existing ancillary data packets must be blank (200 h ) video signal before gs1503b (no existing audio data packets) sav blank (200 h ) eav video signal before gs1503b (with existing audio data packets) sav audio group 1 audio group 2 blank (200 h ) eav video signal after gs1503b insertion of audio groups 1 & 2 (cascade = 0) sav audio group 1 (new) audio group 2 (new) eav ln crc ln crc ln crc blank (200 h ) eav video signal before gs1503b (with existing audio data packets) sav audio group 1 audio group 2 blank (200 h ) eav video signal after gs1503b insertion of audio groups 3 & 4 (cascade = 1) sav audio group 1 (old) audio group 2 (old) audio group 3 (new) audio group 4 (new) ln crc ln crc
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 38 of 90 contiguous from the beginning of the hanc space or the gs1503b will overwrite existing packets with blanking before multiplexing new packets. see figure 4-19 . figure 4-19: insertion of audio groups 3 & 4 with space between eav and audio 4.10 audio control packets 4.10.1 audio control packet structure figure 4-20 shows the structure of the audio control packet as defined in smpte 299m. an audio control packet is multiplexed once per field in the luma channel of the video data stream. table 4-29 lists descriptions of the individual audio control packet words. the gs1503b will automatically generate certain audio control packet words. figure 4-20: audio control packet structure blank (200 h ) blank (200 h ) eav video signal before gs1503b (with space between eav and existing audio data packets) sav audio group 1 audio group 2 video signal after gs1503b insertion of audio groups 3 & 4 (cascade = 1) blank (200 h ) eav sav audio group 3 (new) audio group 4 (new) ln crc ln crc adf user data words 10-bit did dbn dc af del1-2 del3-4 rsrv cs rate act
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 39 of 90 4.10.2 audio control packet did setting to multiplex audio control packets for audio channels 1 to 4 (inputs ain1/2 and ain3/4), the ctrona bit 2 of host interface register 02fh must be set high. to multiplex audio control packets for audio channels 5 to 8 (inputs ain5/6 and ain7/8), the ctronb bit 2 of host interface register 020h must be set high. the audio control packet group did for audio in put channels 1 to 4 is set in ctrida[1:0] bits 1-0 of host interface register 02fh. the audio control packet group did for audio input channels 5 to 8 is set in ctridb[1:0] bits 3-2 of host interface register 020h. table 4-30 shows the 2-bit host interface setting for the corresponding audio control packet group did. when cascade is set low (external pin or register), the gs1503b will default to audio groups 1 and 2, where the audio control packet for ain1/2 and ain3/4 will be multiplexed with group 1 did, and ain5/6 and ain7/8 with group 2 did. control packet data can be programmed via the corresponding registers in the host interface. table 4-29: audio control packet word descriptions name no of words description data auto-generation adf 3 ancillary data flag 000h 3ffh 3ffh yes did 1 audio group data id 1e3h 2e2h 2e1h 1e0h see table 4-30 in section 5.8.2 dbn 1 data block number 200h yes dc 1 data count 10bh yes af 1 audio frame number C 9-bit host interface setting rate 1 sampling frequency C 4-bit host interface setting act 1 active channel C chact[7:0] setting del1-2 3 ch1/2 delay data C 26-bit host interface setting del3-4 3 ch3/4 delay data C 26-bit host interface setting rsrv 2 reserved words 200h 18-bit host interface setting cs 1 checksum. calculates the sum of lower 9 bits of 15 words from did Cyes
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 40 of 90 table 4-30: audio control packet group did host interface settings audio group 10-bit data host interface register setting (2-bit) 1 1e3h 11b 2 2e2h 10b 3 2e1h 01b 4 1e0h 00b table 4-31: register settings name description address bit setting default ctrona ch1-4 audio control packet multiplex enable (1: enabled) 02f 2 1 1 ctrida[1:0] ch1-4 audio control packet did set 02f 1-0 see table 4-30 11b af_noa[8:0] ch1-4 audio frame number 030 031 0 7-0 C0 ratea[2:0] ch1-4 sampling frequency data 032 3-1 C 0 asxa ch1-4 synchronization (0:synchronous; 1: non-synchronous) 032 0C 0 del1-2a[25:0] ch1/2 delay data 033 034 035 036 1-0 7-0 7-0 7-0 C0 del3-4a[25:0] ch3/4 delay data 037 038 039 03a 1-0 7-0 7-0 7-0 C0 rsrva[17:0] ch1-4 reserved words 03b 03c 03d 1-0 7-0 7-0 C0 ctronb ch5-8 audio control packet multiplex enable (1:enabled) 020 2 1 1 ctridb[1:0] ch5-8 audio control packet did set 020 1-0 see table 4-30 10b af_nob[8:0] ch5-8 audio frame number 021 022 0 7-0 C0 rateb[2:0] ch5-8 sampling frequency data 023 3-1 C 0 asxb ch5-8 synchronization (0:synchronous; 1: non-synchronous) 023 0C 0
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 41 of 90 4.11 arbitrary data packets the gs1503b can multiplex arbitrary data packets according to smpte 291m. typically, this consists of linear time code (ltc), vertical interval time code (vitc) or other user data, which is multiplexed once per video field. the gs1503b has two modes in which arbitrary data can be multiplexed into the luma channel of the video data stream. a maximum of 255 user data words can be multiplexed in one packet. figure 4-21 shows the structure of the arbitrary data packet. note: arbitrary data packets will not be mu ltiplexed in the two lines following the video switching point (see video switching line setting on page 35 ). figure 4-21: arbitrary data packet structure del1-2b[25:0] ch5/6 delay data 024 025 026 027 1-0 7-0 7-0 7-0 C0 del3-4b[25:0] ch7/8 delay data 028 029 02a 02b 1-0 7-0 7-0 7-0 C0 rsrvb[17:0] ch5-8 reserved words 02c 02d 02e 1-0 7-0 7-0 C0 table 4-31: register settings name description address bit setting default adf user data words msb did sdid dc udw0[100] cs contents set in host interface registers udw254[1fe] udw253[1fd] udw252[1fc] udw251[1fb] udw1[101] udw2[102] udw3[103] lsb not b8 parity bit
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 42 of 90 4.11.1 arbitrary data multiplexing in external pin mode this is the default mode for multiplexing arbitrary data packets. the gs1503b will set the pkteno external pin high when arbitrary data can be input to the device. two vclk cycles after pkteno goes high, the us er should set the pkten arbitrary packet enable pin high. two vclk cycles after pkten is set high, arbitrary data can be input at the pkt[7:0] bus. see figure 4-22 for timing. the user is required to enter the following arbitrary data: data id (did), secondary data id (sdid), data count (dc) and user data words (udw: maximum of 255), via the pkt[7-0] pins. this gs1503b automatically generates the ancillary data flag (adf), checksum (cs) and bit 8 (parity bit) and bit 9 (not bit 8). the pkteno pin will be set high on all vi deo lines except the two lines following the video switching point. for example, with the default setting of line 7 field 1, pkteno will not be set high on lines 8 and 9. the switching point is set in the sw_lna[12:0] and sw_lnb[12:0] host interface registers for field 1 and field 2 respectively. see video switching line setting on page 35 . figure 4-22: arbitrary data packet input timing diagram y/c b /c r [19:0] vin[19:0] gs1503b pkteno pkten pkt[7:0] arbitrary data packet timing arbitrary data input enable arbitrary data vclk pkt[7:0] 2 clks 2 clks 2 clks 2 clks arbitrary data pkteno pkten automatically generated by the gs1503b udw254 udw253 udw252 udw251 udw250 cs udw3 udw2 udw1 udw0 dc sdid did adf adf adf arbitrary packet
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 43 of 90 4.11.2 arbitrary data multiplexing in host interface mode to select this mode, set arbitmode bit 0 in host interface register 050h high. in this mode, the did, sdid, dc and user data words must be programmed via the corresponding host interface registers. set the video line number for field 1 and field 2 in which the arbitrary data packets are to be multiplexed using the arbitlinea[11:0] and arbitlineb[11:0] host interface registers respectively. the arbitrary data packet is multiplexed when arbiton bit 1 in host interface register 050h is set high. arbiton should be set low during the programming of the arbitrary data packet in the host interface. arbitlinea[11:0] and arbitlineb[11:0] should not be set to the two line numbers following the line number set in the sw_lna[12:0] and sw_lnb[12:0] host interface registers. for example, with the default setting of line 7 field 1, arbitlinea[11:0] should not be set to line 8 or 9. table 4-32: register settings name description address bit setting default arbiton arbitrary packet multiplex enable (1: enabled) valid only when arbitmode is high 050 1 1 0 arbitmode arbitrary packet mode selection (0: external pin mode; 1: host mode) 050 01 0 arbitdid[7-0] arbitrary packet did setting 051 7-0 C 0 arbitsdid[7-0] arbitrary packet sdid setting 052 7-0 C 0 arbitdc[7-0] arbitrary packet dc setting 053 7-0 C 0 arbitlinea[11:0] field 1 multiplexing line 054 055 3-0 7-0 C0 arbitlineb[11:0] field 2 multiplexing line 056 057 3-0 7-0 C0 arbitudw arbitrary packet udw setting 100-1fe 7-0 C 0 table 4-33: multiplex mode host interface registers control item name description address bit r/w default video vm_sel video input format (external pin/internal register) configuration select. when set low, the video input format is configured via the vm[3:0] pins. when set high, the video input format is configured via the "vm[3:0]" bits. 000 7 r/w 0 video_det video signal detection flag. set high when 3 consecutive trs are detected in the input video signal. 000 6r 0
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 44 of 90 crc_err video input signal crc error detection. set high when a crc error is detected in the input video signal. this register is refreshed on every video frame. 000 5r 0 crc_ins video crc insertion. when set high, the luma and chroma line crc words are re-calculated and inserted into the output video signal. 000 4r/w 1 vm[3:0] video input format selection. see table 4-1 . valid when "vm_sel" is high. 000 3-0 r/w 0 ext_sel external exth/extf input select. when set low, the exth and extf pins are configured as outputs. when set high, the gs1503b will insert trs and line numbers based on signals input at the exth and extf pins. 001 3 r/w 0 scrbypass scramble processing bypass select. when set high, the internal scrambler and nrz(i) encoder is bypassed. note: the status of the scrbypass external pin is not updated in this register. the value programmed in this register is logical or'd with the scrbypass external pin setting. 001 2r/w 0 8bit_sel 8-bit input selection. when set high, the gs1503b will accept an 8-bit input video signal. 001 1r/w 0 dscbypass descramble process bypass select. when set high, the internal smpte 292m descrambler is bypassed. note: the status of the dscbypass external pin is not updated in this register. the value programmed in this register is logical or'd with the dscbypass external pin setting. 001 0r/w 0 sw_lnb[12:0] video field 2 switching line setting. designates the video switching point for field 2. the default line number is 569, as defined by smpte 299m. 002 003 4-0 7-0 r/w 569d sw_lna[12:0] video field 1 switching line setting. designates the video switching point for field 1. the default line number is 7, as defined by smpte 299m. 004 005 4-0 7-0 r/w 7d crc_cnt[11:0] crc error accumulation. reports the accumulated number of crc errors in one video frame. 006 007 3-0 7-0 r0 rsv not used. 008 7-5 C 0 limit_on illegal code re-mapping select. when set high, input video words between 000-003 are re-mapped to 004, and values between 3fc-3ff are re-mapped to 3fb. valid only when "ext_sel" is set high. 008 4 r/w 0 table 4-33: multiplex mode host interface registers (continued) control item name description address bit r/w default
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 45 of 90 vblk_ins vertical blanking enable. when set high, the output video vertical blanking will be set to 040h for the luma channel and 200h for the chroma channel. 008 3 r/w 0 hblk_ins horizontal blanking enable. when set high, the output video horizontal blanking, including trs, line numbers and line crc words, will be set to 040h for the luma channel and 200h for the chroma channel. note: if blanking of line numbers and trs words is required, ln_ins and trs_ins must be set low. 008 2 r/w 0 ln_ins line insertion enable. when set high, the gs1503b will insert line numbers into the video data stream. when set low, existing line numbers will remain in the output video stream. 008 1 r/w 1 trs_ins trs insertion enable. when set high, the gs1503b will insert trs codes into the video data stream. when set low, existing trs codes will remain in the output video stream. 008 0 r/w 1 audio am_sel audio input format (external pin/register) configuration select. when set low, the audio input format is configured via the am[1:0] pins. when set high, the audio input format is configured via the "am[1:0]" bits. 010 7 r/w 0 aud7/8_det ch7/8 audio input signal detection. when set high, an audio signal has been detected at the ain7/8 input pin. 010 6r 0 aud5/6_det ch5/6 audio input signal detection. when set high, an audio signal has been detected at the ain5/6 input pin. 010 5r 0 aud3/4_det ch3/4 audio input signal detection. when set high, an audio signal has been detected at the ain3/4 input pin. 010 4r 0 aud1/2_det ch1/2 audio input signal detection. when set high, an audio signal has been detected at the ain1/2 input pin. 010 3r 0 rsv not used. 010 2C 0 am[1:0] audio input format select. see table 4-16 . valid when "am_sel" is high. 010 1-0 r/w 0 acrc7/8_ins ch7/8 audio channel status crc insertion. when set high, the ch7/8 audio input channel status crc is re-calculated before being multiplexed into the audio data packet. valid only when aes/ebu audio input format is selected. 011 7 r/w 0 table 4-33: multiplex mode host interface registers (continued) control item name description address bit r/w default
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 46 of 90 acrc5/6_ins ch5/6 audio channel status crc addition. when set high, the ch5/6 audio input channel status crc is re-calculated before being multiplexed into the audio data packet. valid only when aes/ebu audio input format is selected. 011 6r/w 0 acrc3/4_ins ch3/4 audio channel status crc addition. when set high, the ch3/4 audio input channel status crc is re-calculated before being multiplexed into the audio data packet. valid only when aes/ebu audio input format is selected. 011 5r/w 0 acrc1/2_ins ch1/2 audio channel status crc addition. when set high, the ch1/2 audio input channel status crc is re-calculated before being multiplexed into the audio data packet. valid only when aes/ebu audio input format is selected. 011 4r/w 0 acs7/8_err ch7/8 audio channel status error detection. when set high, a channel status crc error has been detected in the ch7/8 audio input. valid only when aes/ebu audio input format is selected. 011 3r 0 acs5/6_err ch5/6 audio channel status error detection. when set high, a channel status crc error has been detected in the ch5/6 audio input. valid only when aes/ebu audio input format is selected. 011 2r 0 acs3/4_err ch3/4 audio channel status error detection. when set high, a channel status crc error has been detected in the ch3/4 audio input. valid only when aes/ebu audio input format is selected. 011 1r 0 acs1/2_err ch1/2 audio channel status error detection. when set high, a channel status crc error has been detected in the ch1/2 audio input. valid only when aes/ebu audio input format is selected. 011 0r 0 ap7/8_err ch7/8 audio parity error detection. when set high, an audio parity error has been detected in the ch7/8 audio input. valid only when aes/ebu audio input format is selected. 012 3 r 0 ap5/6_err ch5/6 audio parity error detection. when set high, an audio parity error has been detected in the ch5/6 audio input. valid only when aes/ebu audio input format is selected. 012 2r 0 ap3/4_err ch3/4 audio parity error detection. when set high, an audio parity error has been detected in the ch3/4 audio input. valid only when aes/ebu audio input format is selected. 012 1r 0 table 4-33: multiplex mode host interface registers (continued) control item name description address bit r/w default
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 47 of 90 ap1/2_err ch1/2 audio parity error detection. when set high, an audio parity error has been detected in the ch1/2 audio input. valid only when aes/ebu audio input format is selected. 012 0r 0 audio channel status block audio_cs[7:0] : audio_cs [183:176] audio channel status set. valid in serial audio input modes. used to enter the 23 8-bit bytes of the audio channel status block, as defined in aes3-1992. note: the crc byte is generated internally by the gs1503b. 058 : 06e 7-0 : 7-0 r/w see table 4-34 audio data packet chact[7-0] audio channel multiplex enable. when set high, the corresponding audio channel is multiplexed into the chroma video data stream. "chact[7]" corresponds to audio input channel 8 and "chact[0]" corresponds to audio input channel 1. when all bits are set low, no audio data packets will be multiplexed and the gs1503b will be in bypass mode. 013 7-0 r/w ffh cascade cascade select. when set high, the gs1503b will default to audio groups 3 and 4. when set low, the gs1503b will default to audio groups 1 and 2. note: the status of the cascade external pin is not updated in this register. the value programmed in this register is logical or'd with the cascade external pin setting. 014 7 r/w 0 rsv not used. 014 6C C amuteb ch5-8 audio mute enable. when set high, the multiplexed audio packets for audio channels 5 to 8 are forced to zero. note: the status of the mute external pin is not updated in this register. the value programmed in this register is logical or'd with the mute external pin setting. 014 5r/w 0 amutea ch1-4 audio mute enable. when set high, the multiplexed audio packets for audio channels 1 to 4 are forced to zero. note: the status of the mute external pin is not updated in this register. the value programmed in this register is logical or'd with the mute external pin setting. 014 4r/w 0 dataidb[1:0] ch5-8 audio group did setting. designates the audio group did for audio channels 5 to 8. see table 4-23 . when cascade (external pin or register) is set low, the default setting is audio group 2. when cascade is set high, the default setting is audio group 4. 014 3-2 r/w 10b table 4-33: multiplex mode host interface registers (continued) control item name description address bit r/w default
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 48 of 90 dataida[1:0] ch1-4 audio group did setting. designates the audio group did for audio channels 1 to 4. see table 4-23 . when cascade (external pin or register) is set low, the default setting is audio group 1. when cascade is set high, the default setting is audio group 3. 014 1-0 r/w 11b audio control packet rsv not used. 020 7-3 C 0 ctronb ch5-8 audio control packet multiplex enable. when set high, the audio control packets for audio channels 5 to 8 will be multiplexed into the luma channel of the video data stream. 020 2r/w 1 ctridb[1:0] ch5-8 audio control packet did setting. designates the audio control packet did for audio channels 5 to 8. see table 4-30 . the default setting is audio group 2. 020 1-0 r/w 10b af_nob[8:0] ch5-8 audio frame number. designates the audio frame number for audio channels 5 to 8. will be multiplexed into the audio control packet as per smpte 299m. 021 022 0 7-0 r/w 0 rateb[2:0] ch5-8 sampling frequency set. designates the audio sampling frequency for audio channels 5 to 8. will be multiplexed into the rate word of the audio control packet as per smpte 299m. the default setting is 48khz. 023 3-1 r/w 0 asxb ch5-8 synchronization set. when set high, the "asx" bit of the audio control packet rate word designates audio channels 5 to 8 as asynchronous, as per smpte 299m. when set low, the "asx" bit of the audio control packet rate word designates synchronous audio (default setting). 023 0r/w 0 del1-2b[25:0] ch5/6 delay data. designates the accumulated audio processing delay relative to video for audio channels 5 and 6. will be multiplexed into the audio control packet as per smpte 299m. 024 025 026 027 1-0 7-0 7-0 7-0 r/w 0 del3-4b[25:0] ch7/8 delay data. designates the accumulated audio processing delay relative to video for audio channels 7 and 8. will be multiplexed into the audio control packet as per smpte 299m. 028 029 02a 02b 1-0 7-0 7-0 7-0 r/w 0 rsrvb[17:0] ch5-8 reserve words. designates the value set in the rsrv words of the audio control packet for audio channels 5 to 8, as per smpte 299m. note: as these words are reserved for future use, they should be set to zero. 02c 02d 02e 1-0 7-0 7-0 r/w 0 table 4-33: multiplex mode host interface registers (continued) control item name description address bit r/w default
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 49 of 90 rsv not used. 02f 7-3 C 0 ctrona ch1-4 audio control packet multiplex enable. when set high, the audio control packets for audio channels 1 to 4 will be multiplexed into the luma channel of the video data stream. 02f 2r/w 1 ctrida[1:0] ch1-4 audio control packet did setting. designates the audio control packet did for audio channels 1 to 4. see table 4-30 . the default setting is audio group 1. 02f 1-0 r/w 11b af_noa[8:0] ch1-4 audio frame number. designates the audio frame number for audio channels 5 to 8. will be multiplexed into the audio control packet as per smpte 299m. 030 031 0 7-0 r/w 0 ratea[2:0] ch1-4 sampling frequency set. designates the audio sampling frequency for audio channels 1 to 4. will be multiplexed into the rate word of the audio control packet as per smpte 299m. the default setting is 48khz. 02f 3-1 r/w 0 asxa ch1-4 synchronization set. when set high, the "asx" bit of the audio control packet rate word designates audio channels 1 to 4 as asynchronous, as per smpte 299m. when set low, the "asx" bit of the audio control packet rate word designates synchronous audio (default setting). 02f 0 r/w 0 del1-2a[25:0] ch1/2 delay data. designates the accumulated audio processing delay relative to video for audio channels 1 and 2. will be multiplexed into the audio control packet as per smpte 299m. 033 034 035 036 1-0 7-0 7-0 7-0 r/w 0 del3-4a[25:0] ch3/4 delay data. designates the accumulated audio processing delay relative to video for audio channels 3 and 4. will be multiplexed into the audio control packet as per smpte 299m. 037 038 039 03a 1-0 7-0 7-0 7-0 r/w 0 rsrva[17:0] ch1-4 reserve words. designates the value set in the rsrv words of the audio control packet for audio channels 1 to 4, as per smpte 299m. note: as these words are reserved for future use, they should be set to zero. 03b 03c 03d 1-0 7-0 7-0 r/w 0 arbitrary data packet arbiton arbitrary data packet multiplex. valid only when "arbitmode" is high. when set high, arbitrary data packets will be multiplexed into the luma video data stream using the host interface register settings. 050 1 r/w 0 table 4-33: multiplex mode host interface registers (continued) control item name description address bit r/w default
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 50 of 90 arbitmode arbitrary packet mode select. when set high, arbitrary data packets are multiplexed using the host interface register settings. when set low, arbitrary data packets are multiplexed using the external pin inputs. 050 0 r/w 0 arbitdid[7:0] arbitrary packet data id setting. designates the 8 lsbs of the arbitrary data packet did word. the 2 msbs are internally generated. "arbitdid[7]" is the msb and "arbitdid[0]" is the lsb. valid only when "arbitmode" is high. 051 7-0 r/w 0 arbitsdid[7:0] arbitrary packet secondary data id setting. designates the 8 lsbs of the arbitrary data packet secondary did word. the 2 msbs are internally generated. "arbitsdid[7]" is the msb and "arbitsdid[0]" is the lsb. valid only when "arbitmode" is high. 052 7-0 r/w 0 arbitdc[7:0] arbitrary packet dc setting. designates the 8 lsbs of the arbitrary data packet data count word. the 2 msbs are internally generated. "arbitdc[7]" is the msb and "arbitdc[0]" is the lsb. valid only when "arbitmode" is high. 053 7-0 r/w 0 arbitlineb[11:0] field 2 arbitrary packet multiplex line number setting. designates the field 2 video line in which the arbitrary data packets will be multiplexed. valid only when "arbitmode" is high. 054 055 3-0 7-0 r/w 0 arbitlinea[11:0] field 1 arbitrary packet multiplex line number setting. designates the field 1 video line in which the arbitrary data packets will be multiplexed. valid only when "arbitmode" is high. 056 057 3-0 7-0 r/w 0 arbitudw0 : arbitudw254 arbitrary packet user data word set. designates the 8 lsbs for each of the 255 arbitrary packet user data words. the 2 msbs are internally generated. valid only when "arbitmode" is high. 100 : 1fe 7-0 : 7-0 r/w 0 table 4-33: multiplex mode host interface registers (continued) control item name description address bit r/w default table 4-34: audio channel status default values address value channel status 058 85 professional; valid audio; no emphasis (manual override disabled); 48khz sampling frequency (manual override disabled). 059 08 two-channel mode (manual override disabled).
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 51 of 90 05a 2c maximum audio sample word length is 24bits; encoded audio word length is 24-bit. others 00 C table 4-34: audio channel status default values address value channel status
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 52 of 90 5. demultiplex mode 5.1 functional overview the gs1503b hd embedded audio codec fully supports the demultiplexing of audio data packets, audio control packets and ar bitrary data packets as per smpte 291m and 299m. the device can be configured to operate with all video standards defined in smpte 292m, levels a through m. the gs1503b also supports the 1080/24psf, 25psf and 30psf video formats as described in smpte rp211. the video input format can be one of the following configurations: ?10-bit y and c b /c r input with trs and line numbers ?20-bit scrambled input the video output format can be one of the following configurations: ?20-bit scrambled output ?10-bit y and c b /c r output up to a maximum of 8 channels of 48khz digital audio can be demultiplexed per device. the audio output format can be selected as either aes/ebu, or one of two serial audio data output modes. a maximum of 16 channels of audio can be demultiplexed by cascading two devices in parallel. audio control packets, as defined in smpte 299m, can also be demultiplexed to obtain information about the nature of the embedded audio data. the contents of the audio control packet are stored in registers of the host interface. the gs1503b will also demultiplex arbitrary data packets as defined in smpte 291m. the arbitrary data packets can serve as an auxiliary data signal for proprietary applications. the gs1503b can be configured to demultiplex arbitrary data packets and output them at dedicated external pins or via the host interface registers. up to a maximum of 255 8-bit words can be demultiplexed (excluding ancillary data flags and checksum). to use the gs1503b in demultiplex mode, set the mux /demux external pin high.
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 53 of 90 5.2 video standard the video standard is selected from the vm[3:0] external pins or vm[3:0] bits 3-0 in host interface register 000h. to configure the video standard via the host interface, vm_sel bit 7 in host interface register 000h must be set high. the gs1503b will default to the vm[3:0] external pin setting. the supported video standards are listed in table 5-1 . table 5-1: supported video standards vm [3:0] input format reference smpte document smpte 292m level 1110b 1035i (30 & 30/1.001 hz) 260m a, b 1100b 1080i (25 hz) 295m c 1000b 1080i/1080sf (30 & 30/1.001 hz) 274m, rp211 d, e 1010b 1080i/1080sf (25 hz) 274m, rp211 f 1111b 1080sf (24 & 24/1.001 hz) rp211 0010b 1080p (30 & 30/1.001 hz) 274m g, h 0100b 1080p (25 hz) 274m i 0110b 1080p (24 & 24/1.001 hz) 274m j, k 0000b 720p (60 & 60/1.001 hz) 296m l, m 0001b 720p (30 & 30/1.001 hz) 296m 0011b 720p (50 hz) 296m 0101b 720p (25 hz) 296m 0111b 720p (24 & 24/1.001 hz) 296m all other settings are reserved table 5-2: register settings name description address bit setting default vm_sel 0: external pin select 1: register select 000 7 1 0 vm[3:0] video formal selection (vm[3] is msb) 000 3-0 see table 5-1 0
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 54 of 90 5.3 video input format 5.3.1 20-bit scrambled input figure 5-1: 20-bit scrambled input configuration y/c b /c r [19:0] vin[19:0] dscbypass gs1503b table 5-3: register settings (default mode) name description address bit setting default ext_sel 0: exth/extf output select 1: exth/extf input select 001 3 0 0 8bit_sel 0: 10-bit mode select 1: 8-bit mode select 001 10 0 dscbypass 0: descrambling enabled 1: bypass descrambling 001 00 0
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 55 of 90 5.3.2 10-bit y and c b /c r input with trs and line numbers figure 5-2: 10-bit y and c b /c r input with trs and line numbers configuration figure 5-3: video input format (10-bit with trs and line numbers) y[9:0] c b /c r [9:0] vin[19:10] vin[9:0] dscbypass extf exth gs1503b +3.3v vn y, c b /c r v0 video 0 3 8 4 vclk exth extf 3ff 3ff xyz 000 000 000 000 xyz 10-bit ln1 ln0 crc0 crc1 table 5-4: register settings name description address bit setting default ext_sel 0: exth/extf output select 1: exth/extf input select 001 3 0 0 8bit_sel 0: 10-bit mode select 1: 8-bit mode select 001 10 0 dscbypass 0: descrambling enabled 1: bypass descrambling 001 01 0
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 56 of 90 5.4 video output format 5.4.1 10-bit y and c b /c r output figure 5-4: 10-bit y and c b /c r output configuration 5.4.2 20-bit scrambled output figure 5-5: 20-bit scrambled output configuration y[9:0] c b /c r [9:0] vout[19:10] vout[9:0] scrbypass gs1503b +3.3v table 5-5: register settings name description address bit setting default scrbypass 0: smpte 292m scrambling enabled 1: bypass smpte 292m scrambling 001 2 1 0 y/c b /c r [19:0] vout[19:0] scrbypass gs1503b
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 57 of 90 5.5 video data processing 5.5.1 video signal input detection the gs1503b will set the video_det external pin high when three consecutive trs are detected in the input video signal. also, the video_det bit of host interface register 000h is set high. 5.5.2 video input crc error detection the gs1503b will set the crc_err external pin high when a crc error is detected in the input video signal. also, the crc_err bit 5 of host interface register 000h is set high. the number of crc errors accumulated in one video frame can be read form crc_cnt[11:0] in host interface registers 006h and 007h. table 5-6: register settings (default mode) name description address bit setting default scrbypass 0: smpte 292m scrambling enabled 1: bypass smpte 292m scrambling 001 2 0 0 table 5-7: register settings name description address bit setting default video_det video input signal detection (1: detection) 000 6 C 0 table 5-8: register settings name description address bit setting default crc_err video input signal crc error detection (1: detection) 000 5 C 0 crc_cnt[11:0] video input signal crc error accumulation in 1 video frame 006 007 3-0 7-0 C0
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 58 of 90 5.5.3 video output crc insertion when the crc_ins bit 4 of host interface register 000h is set high, the gs1503b will re-calculate the video line crc words. the re-calculated crc words are inserted in the video output signal. when crc_ins is set low, the line crc words are not updated and existing crc words at the input of the device will be output unchanged. 5.5.4 input blanking when vblk_ins bit 3 of host interface register 008h is set high, the input video vertical blanking will be set to 040h for the luma channel and 200h for the chroma channel. when hblk_ins bit 2 of host interface register 008h is set high, the input video horizontal blanking will be set to 040h for the luma channel and 200h for the chroma channel. the trs, line number and crc words will also be set to blanking values. the blanking function is performed at the output of the gs1503b video data stream. if the hblk_ins bit is set high, any embedded audio or control packets will be replaced with blanking codes. the gs1503b will demultiplex data contained in the packets, prior to the blanking function, and output at the corresponding pins. 5.5.5 line number insertion when ln_ins bit 1 of host interface register 008h is set high, the gs1503b will insert line numbers into the video data stream. when set low, existing line numbers will remain in the output video stream. table 5-9: register settings name description address bit setting default crc_ins video line crc insertion (1: insertion) 000 4 1 1 table 5-10: register settings name description address bit setting default vblk_ins input vertical blanking (1: enabled) 008 3 1 0 hblk_ins input horizontal blanking (1: enabled) 008 210 table 5-11: register settings name description address bit setting default ln_ins line number insertion (1: enabled) 008 1 1 1
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 59 of 90 5.5.6 trs word insertion when trs_ins bit 0 of host interface register 008h is set high, the gs1503b will insert trs codes into the video data stream. when set low, existing trs codes will remain in the output video stream. 5.6 audio data processing 5.6.1 digital audio output format the gs1503b has two audio output formats, aes/ebu digital audio output and serial output, as listed in table 5-13 . the serial audio output can be formatted in the following two modes. see figure 5-6 : ? 24-bit left justified; msb first ? 24-bit right justified; msb last the audio output format is configured using the am[1:0] external pins or via am[1:0] bits 1-0 in host interface register 010h. to configure the audio output format via the host interface, am_sel bit 7 in host interface register 010h must be set high. the gs1503b will default to the am[1:0] external pin setting. note: when configured in aes/ebu audio mode, the gs1503b will not output a 48khz (fs) word clock at the wcouta and wcoutb pins. table 5-12: register settings name description address bit setting default trs_ins trs word insertion (1: enabled) 008 0 1 1 table 5-13: audio output formats am[1:0] audio output format 0 serial audio output: 24-bit left justified; msb first 1 serial audio output: 24-bit right justified; msb last 2 aes/ebu audio output table 5-14: register settings name description address bit setting default am_sel 0: external pin setting 1: register setting 010 7 1 0 am[1:0] audio output format selection (am[1] is msb) 010 1-0 see table 5-13 0
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 60 of 90 figure 5-6: audio output formats 5.6.2 digital audio output timing 5.6.2.1 aes/ebu format output a 6.144mhz (128fs) audio clock must be supplied to the aclka and aclkb inputs. aclka is used to clock aes/ebu digital audio signal for channels 1 to 4 (aout1/2 and aout3/4). aclkb is used to clock aes/ebu digital audio signal for channels 5 to 8 (aout5/6 and aout7/8). in aes/ebu output mode, the audio word clock inputs wcinb and wcinb should be grounded. see figure 5-7 for timing. the user can access the audio channel status block information via the audio_cs[183:0] bits in host interface registers 058h to 06eh. to read the audio channel status information, the cs_mode bit 3 of host interface register 06fh should be set high. the embedded audio channel from which the channel status information is to be extracted is set in the ch_sel[2:0] bits 2-0 of host interface register 06fh. the ch_sel[2:0] setting for audio channel 1 is 000b, through to 111b for channel 8. the cs_rqst bit must be set high to begin the process of extracting the audio channel status information. once extracted, the gs1503b will set cs_wend bit high and the user can access the data for host interface registers 058h to 06eh. when cs_mode is set low, the audio channel status information in the aes/ebu audio outputs will be replaced with data programmed in the audio_cs[183:0] bits of host interface registers 058h to 06eh. 23 channel 1 msb channel 2 wcouta/wcoutb 0 0 lsb 23 23 msb 0 0 lsb 23 mode1 mode0 mode2 (aes/ebu) sync preamble 24-bit audio sample word vucp 0 3 4 2728293031 channel status bit validity bit user data bit parity bit sync preamble 24-bit audio sample word vucp 0 3 4 2728293031 table 5-15: register settings name description address bit setting default cs_wend audio channel status write flag (1: data ready) 06f 5 C 0 cs_rqst audio channel status request (1: enable) 06f 410
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 61 of 90 figure 5-7: aes/ebu audio output configuration and timing cs_mode 0: audio channel status replace 1: audio channel status demultiplex 06f 310 ch_sel[2:0] audio channel status select 06f 2-0 C 000b table 5-15: register settings name description address bit setting default y/c b /c r [19:0] vin[19:0] aout5/6 gs1503b aout1/2 aout3/4 aout7/8 aclka aclkb audio channels 1 & 2 audio channels 3 & 4 audio channels 5 & 6 audio channels 7 & 8 6.144mhz (128 fs) 6.144mhz (128 fs) aclka/b aout1/2, aout3/4 aout5/6, aout7/8 6.144mhz
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 62 of 90 5.6.2.2 serial audio output modes a 6.144mhz (128fs) audio clock must be supplied to the aclka and aclkb inputs. an audio word clock at 48khz (fs) will be output at the wcouta and wcoutb external pins, as shown in figure 5-8 . the user can access the audio channel status block information via the audio_cs[183:0] bits in host interface registers 058h to 06eh. to read the audio channel status information, the cs_mode bit 3 of host interface register 06fh should be set high. the embedded audio channel from which the channel status information is to be extracted is set in the ch_sel[2:0] bits 2-0 of host interface register 06fh. the ch_sel[2:0] setting for audio channel 1 is 000b, through to 111b for channel 8. the cs_rqst bit must be set high to begin the process of extracting the audio channel status information. once extracted, the gs1503b will set cs_wend bit high and the user can access the data for host interface registers 058h to 06eh. when dec_mode (external pin or register setting) is set low, the audio word clock inputs wcinb and wcinb should be grounded. figure 5-8: serial audio output configuration and timing y/c b /c r [19:0] vin[19:0] aout5/6 gs1503b aout1/2 aout3/4 aout7/8 aclka aclkb audio channels 1 & 2 audio channels 3 & 4 audio channels 5 & 6 audio channels 7 & 8 6.144mhz (128 fs) 6.144mhz (128 fs) aclka/b aout1/2, aout3/4 aout5/6, aout7/8 64 clks 48khz (fs) 48khz (fs) wcouta wcoutb wcouta/b 64 clks
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 63 of 90 5.6.3 audio clock phase locked loop figure 5-9 shows the configuration for deriving the 6.144mhz audio clock in aes/ebu and serial audio output modes. the gs1503b will internally synchronize the audio output to the corresponding aclk. this conf iguration is not required when dec_mode is set high. figure 5-9: block diagram of gs1503b audio clock pll y/c b /c r [19:0] vin[19:0] aout5/6 gs1503b aout1/2 aout3/4 aout7/8 aclka aclkb audio channels 1 & 2 audio channels 3 & 4 audio channels 5 & 6 audio channels 7 & 8 6.144mhz (128 fs) pllcnta pllcntb low pass filter low pass filter vcxo 24.576mhz vcxo 24.576mhz 4 4 6.144mhz (128 fs)
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 64 of 90 5.6.4 audio data packet detection the audio data packet detect registers will be set high when a corresponding audio group did has been detected in the chroma channel of the input video stream. host interface register 013h, bits 7-4, report the individual audio groups detected. 5.6.5 ecc error detection & correction the gs1503b performs bch(31,25) forward error detection and correction as described in smpte 299m. the error correction for audio data packets with audio group did set in dataida[1:0] is activated when ecca_on bit 0 of host interface register 013h is set high. similarly, error correction for audio data packets with audio group did set in dataidb[1:0] is activated when eccb_on bit 1 of host interface register 013h is set high when a one-bit error is detected in a bit array of the ecc protected region of the audio data packet with audio group did set in dataida[1:0], ecca_err bit 1 in host interface register 015h is set high. when a one-bit error is detected in the ecc protected region of the audio data packet with audio group did set in dataidb[1:0], the eccb_err bit 5 in host interface register 015h is set high. in both cases, the error external pin will also be set high. a bit array is defined as all 24 bits of bit 0. the next bit array is all 24 bits of bit 1, and so on through to bit 7. up to 8 bits in error can be corrected, providing each bit error is in a different bit array. when there are two bits in error in the same 24-bit array, the errors will be detected, but not corrected. when there are more than two bits in error in a single bit array, the errors will not be detected or corrected. the number of audio data packets corrected in one video frame will be reported in the corresponding host interface registers correcta[11:0] and correctb[11:0]. the gs1503b will also report the number of audio data packets which could not be corrected in one video frame in the corresponding host interface registers no_correcta[11:0] and no_correctb[11:0]. table 5-16: register settings name description address bit setting default adpg4_det audio group 4 data packet detection (1:detection) 013 7 C 0 adpg3_det audio group 3 data packet detection (1:detection) 013 6C 0 adpg2_det audio group 2 data packet detection (1:detection) 013 5C 0 adpg1_det audio group 1 data packet detection (1:detection) 013 4C 0
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 65 of 90 5.6.6 audio data packet error detection when the 1-255 count sequence in the data block number (dbn) word of audio data packets with audio group did set in dataida[1:0] is discontinuous, the dbna_err bit 3 of host interface register 015h will be set high. when the1-255 count sequence in the dbn word of audio data packets with au dio group did set in dataidb[1:0] is discontinuous, the dbnb_err bit 7 of host interface register 015h will be set high. the gs1503b will check the parity (bit 8) for the clk, ch1-4 and ecc0-5 words in the embedded audio data packets. when a parity bit error is detected in audio data packets with audio group did set in dataida[1:0], the adpb8a_err bit 2 of host interface register 015h will be set high. when a parity bit error is detected in audio data packets with audio group did set in dataidb[1:0], the adpb8b_err bit 6 of host interface register 015h will be set high. the gs1503b will re-calculate the audio data packets checksum and compare against the embedded checksum word. when a checksum error is detected in audio data packets with audio group did set in dataida[1:0], the adpcsa_err bit 0 of host interface register 015h will be set high. when a checksum error is detected in audio data packets with audio group did set in dataidb[1:0], the adpcsb_err bit 4 of host interface register 015h will be set high. when any of the above errors are detected, the error external pin will also be set high. table 5-17: register settings name description address bit setting default eccb_err ch5-8 audio data packet ecc error detection (1: detection) 015 5 C 0 ecca_err ch1-4 audio data packet ecc error detection (1: detection) 015 1C 0 correctb[11:0] ch5-8 correctable packets in one video frame 016 017 3-0 7-0 C0 no_correctb[11:0] ch5-8 un-correctable packets in one video frame 018 019 3-0 7-0 C0 correcta[11:0] ch1-4 correctable packets in one video frame 01a 01b 3-0 7-0 C0 no_correcta[11:0] ch5-8 un-correctable packets in one video frame 01c 01d 3-0 7-0 C0 eccb_on ch5-8 audio data packet error correction (1: on) 013 1 1 1 ecca_on ch1-4 audio data packet error correction (1: on) 013 01 1
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 66 of 90 5.6.7 audio data packet did setting the audio group did for audio output channels 1 to 4 (aout1/2 and aout3/4) is set in dataida[1:0] bits 1-0 of host interface register 014h. the audio group did for audio output channels 5 to 8 (aout5/6 and aout7/8) is set in dataidb[1:0] bits 3-2 of host interface register 014h. table 5-19 shows the 2-bit host interface setting for the corresponding audio group did. when cascade is set low (external pin or register), the gs1503b will default to audio groups 1 and 2, where aout1/2 and aout3/4 will be demultiplexed from audio data packets with group 1 did, and aout5/6 and aout7/8 will be demultiplexed from audio data packets with group 2 did. table 5-18: register settings name description address bit setting default dbnb_err ch5-8 audio data packet dbn error detection (1:detection) 015 7 C 0 adpb8b_err ch5-8 audio data packet bit8 error detection (1:detection) 015 6C 0 adpcsb_err ch5-8 audio data packet cs error detection (1:detection) 015 4C 0 dbna_err ch1-4 audio data packet dbn error detection (1:detection) 015 3C 0 adpb8a_err ch1-4 audio data packet bit8 error detection (1:detection) 015 2C 0 adpcsa_err ch1-4 audio data packet cs error detection (1:detection) 015 0C 0 table 5-19: audio group did host interface settings audio group 10-bit data host interface register setting (2-bit) 1 2e7h 11b 2 1e6h 10b 3 1e5h 01b 4 2e4h 00b table 5-20: register settings (cascade set low) name description address bit setting default dataida[1-0] ch1-4 audio data packet did setting 014 1-0 see table 5-19 11b dataidb[1-0] ch5-8 audio data packet did setting 014 3-2 10b
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 67 of 90 when cascade is set high (external pin or register), the gs1503b will default to audio groups 3 and 4, where aout1/2 and aout3/4 will be demultiplexed from audio data packets with group 3 did, and aout5/6 and aout7/8 will be demultiplexed from audio data packets with group 4 did. 5.7 demultiplex cascade mode two gs1503b devices can be cascaded in paralle l to allow up to 16 channels of audio to be demultiplexed (only one device requires cascade to be set high). figure 5-10 shows the cascade architecture for a 16-channel system. to configure the gs1503b for cascade mode, the cascade external pin or cascade bit 7 of host interface register 014h is set high. when set high, the gs1503b will default to audio groups 3 and 4. when set low, the gs1503b will default to audio groups 1 and 2. figure 5-10: demultiplexing 16 channels of audio using cascade architecture table 5-21: register settings (cascade set high) name description address bit setting default dataida[1-0] ch1-4 audio data packet did setting 014 1-0 see table 5-19 01b dataidb[1-0] ch5-8 audio data packet did setting 014 3-2 00b y/c b /c r [19:0] vin[19:0] aout5/6 gs1503b aout7/8 audio channels 1 & 2 audio channels 3 & 4 audio channels 5 & 6 audio channels 7 & 8 cascade vout[19:0] audio group 1 audio group 2 aout1/2 aout3/4 y/c b /c r [19:0] vin[19:0] aout5/6 gs1503b aout7/8 audio channels 9 & 10 audio channels 11 & 12 audio channels 13 & 14 audio channels 15 & 16 cascade vout[19:0] audio group 3 audio group 4 aout1/2 aout3/4 y/c b /c r [19:0] +3.3v
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 68 of 90 5.8 audio control packets 5.8.1 audio control packet detection the audio control packet detect registers will be set high when a corresponding audio group did has been detected in the luma channel of the input video stream. host interface register 020h, bits 7-4, report the individual audio groups detected. 5.8.2 audio control packet did setting to demultiplex audio control packets for audio channels 1 to 4 (aout1/2 and aout3/4), the ctrona bit 2 of host interface register 02fh is set high. to demultiplex audio control packets for audio channels 5 to 8 (aout5/6 and aout7/8), the ctronb bit 2 of host interface register 020h is set high. the audio control packet group did for audio output channels 1 to 4 is set in ctrida[1:0] bits 1-0 of host interface register 02fh. the audio control packet group did for audio output channels 5 to 8 is set in ctridb[1:0] bits 3-2 of host interface register 020h. table 5-24 shows the 2-bit host interface setting for the corresponding audio control packet group did. when cascade is set low (external pin or register), the gs1503b will default to audio groups 1 and 2, where audio control packet data for channels 1 to 4 will be demultiplexed from packets with group 1 did, and audio control packet data for channels 5 to 8 will be demultiplexed from packets with group 2 did. control packet data is accessible via the corresponding registers in the host interface. table 5-22: register settings name description address bit setting default cascade cascade enable (1: enabled) 014 7 1 0 table 5-23: register settings name description address bit setting default acpg4_det audio group 4 control packet detection (1: detection) 020 7 C 0 acpg3_det audio group 3 control packet detection (1: detection) 020 6C 0 acpg2_det audio group 2 control packet detection (1: detection) 020 5C 0 acpg1_det audio group 1 control packet detection (1: detection) 020 4C 0
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 69 of 90 table 5-24: audio control packet group did host interface settings audio group 10-bit data host interface register setting (2-bit) 1 1e3h 11b 2 2e2h 10b 3 2e1h 01b 4 1e0h 00b table 5-25: register settings name description address bit setting default ctrona ch1-4 audio control packet demultiplex enable (1: enabled) 02f 2 1 1 ctrida[1:0] ch1-4 audio control packet did set 02f 1-0 see table 5-24 11b af_noa[8:0] ch1-4 audio frame number 030 031 0 7-0 C0 ratea[2:0] ch1-4 sampling frequency data 032 3-1 C 0 asxa ch1-4 synchronization (0: synchronous; 1: non-synchronous) 032 0C 0 del1-2a[25:0] ch1/2 delay data 033 034 035 036 1-0 7-0 7-0 7-0 C0 del3-4a[25:0] ch3/4 delay data 037 038 039 03a 1-0 7-0 7-0 7-0 C0 rsrva[17:0] ch1-4 reserved words 03b 03c 03d 1-0 7-0 7-0 C0 ctronb ch5-8 audio control packet demultiplex enable (1: enabled) 020 2 1 1 ctridb[1:0] ch5-8 audio control packet did set 020 1-0 see table 5-24 10b af_nob[8:0] ch5-8 audio frame number 021 022 0 7-0 C0 rateb[2:0] ch5-8 sampling frequency data 023 3-1 C 0
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 70 of 90 5.9 arbitrary data packets the gs1503b can demultiplex arbitrary data packets according to smpte 291m. typically, arbitrary data packets consist of linear time code (ltc), vertical interval time code (vitc) or other user data, which is multiplexed once per video field. the gs1503b has two modes in which arbitrary data can be demultiplexed from the luma channel of the video data stream. a maximum of 255 user data words can be demultiplexed. figure 5-11 shows the structure of the arbitrary data packet. figure 5-11: arbitrary data packet structure asxb ch5-8 synchronization (0: synchronous; 1: non-synchronous) 023 0C 0 del1-2b[25:0] ch5/6 delay data 024 025 026 027 1-0 7-0 7-0 7-0 C0 del3-4b[25:0] ch7/8 delay data 028 029 02a 02b 1-0 7-0 7-0 7-0 C0 rsrvb[17:0] ch5-8 reserved words 02c 02d 02e 1-0 7-0 7-0 C0 table 5-25: register settings name description address bit setting default adf user data words msb did sdid dc udw0[100] cs contents available in host interface registers udw254[1fe] udw253[1fd] udw252[1fc] udw251[1fb] udw1[101] udw2[102] udw3[103] lsb not b8 parity bit
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 71 of 90 5.9.1 arbitrary data demultip lexing in external pin mode this is the default mode for demultiplexing arbitrary data packets. the gs1503b will set the pkten external pin high before arbitrary data will be output. two vclk cycles after pkten goes high, arbitrary data is output on the pkt[7:0] bus. see figure 5-12 for timing. the following arbitrary data is output on the pkt[7:0] bus: data id (did), secondary data id (sdid), data count (dc) and user data words (udw: up to a maximum of 255 words). figure 5-12: arbitrary data packet output timing diagram 5.9.2 arbitrary data demultiplexing in host interface mode to select this mode, set arbitmode bit 0 in host interface register 050h high. in this mode, the did, sdid, dc and user data words must be programmed in the corresponding host interface registers. set the video line number for field 1 and field 2 from which the arbitrary data packets are to be demultiplexed using the arbitlinea[11:0] and arbitlineb[11:0] ho st interface registers respectively. the arbitrary data packet is demultiplexed when the arbiton bit 1 in host interface register 050h is set high. arbiton should be set low when reading the arbitrary data packet user data words from the arbitudw host interface registers. y/c b /c r [19:0] vin[19:0] gs1503b pkten pkt[7:0] arbitrary data output enable arbitrary data vclk pkt[7:0] 2 clks 2 clks arbitrary data pkten udw254 udw253 udw252 udw251 udw250 cs udw3 udw2 udw1 udw0 dc sdid did adf adf adf arbitrary packet
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 72 of 90 5.10 ancillary data deletion the gs1503b can be configured to delete the embedded ancillary data packets, after demultiplexing. there are two modes for ancillary data deletion. 5.10.1 entire ancillary data deletion when the anci external pin or anci bit 1 of host interface register 040h is set high, all ancillary data packets in both the luma and chroma channel of the input video stream are deleted. the data is replaced with blanking values 040h in the luma channel and 200h in the chroma channel. the del_sel bit 0 of host interface register 040h must be set low. 5.10.2 audio group designation ancillary data deletion when the anci bit 1 of host interface register 040h is set high, and del_sel bit 0 of host interface register 040h is high, only audio data and control packets which are designated in host interface registers 041h will be deleted. to delete the arbitrary data packets, the corresponding did must be set in the ndid[7:0] host interface register 042h. table 5-26: register settings name description address bit setting default arbiton arbitrary packet demultiplex enable (1: enabled) valid only when arbitmode is high 050 1 1 0 arbitmode arbitrary packet mode selection (0: external pin mode; 1: host mode) 050 01 0 arbitdid[7-0] arbitrary packet did setting 051 7-0 C- 0 arbitsdid[7-0] arbitrary packet sdid setting 052 7-0 C 0 arbitdc[7-0] arbitrary packet dc setting 053 7-0 C 0 arbitlinea[11:0] field 1 multiplexing line 054 055 3-0 7-0 C0 arbitlineb[11:0] field 2 multiplexing line 056 057 3-0 7-0 C0 arbitudw arbitrary packet udw 100-1fe 7-0 C 0
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 73 of 90 5.11 demultiplex mode with word clock input some commercially available hd audio embedding modules do not encode the audio word clock phase information correctly in the clk words of the audio data packet. if this clock information is not correctly encoded, the gs1503b will not output the audio data correctly. also, the gs1503b will be unable to reproduce the 48khz audio word clock (fs) at the wcouta and wcoutb pins in serial audio output modes. if the gs1503b is to be used in conjunction with a hd audio module, which encodes audio clock phase information incorrectly, the dec_mode external pin or decmode bit 2 of host interface register 01eh must be set high. when high , an audio word clock synchronous to the original word clock used for embedding must be input at the wcina and wcinb pins. figure 5-13 shows a system example. when the embedded clock phase data for audio channel 1 to 4 is detected as being in error, the muxerra bit 0 of host interface register 01eh will be set high. similarly, when the embedded clock phase data for audio channel 5 to 8 is detected as being in error, the muxerrb bit 1 of host interface register 01eh will be set high. table 5-27: register settings name description address bit setting default anci ancillary data packet delete (1: deletion enabled) 040 1 1 0 del_sel ancillary data packet delete mode select (0: entire data delete; 1: group designated data delete) 040 01 0 adpg4_del audio group 4 data packet delete (1: delete) 041 7 C 0 adpg3_del audio group 3 data packet delete (1: delete) 041 6C 0 adpg2_del audio group 2 data packet delete (1: delete) 041 5C 0 adpg1_del audio group 1 data packet delete (1: delete) 041 4C 0 acpg4_del audio group 4 control packet delete (1: delete) 041 3C 0 acpg3_del audio group 3 control packet delete (1: delete) 041 2C 0 acpg2_del audio group 2 control packet delete (1: delete) 041 1C 0 acpg1_del audio group 1 control packet delete (1: delete) 041 0C 0 ndid[7:0] arbitrary packet did delete setting 042 7-0 C 0 table 5-28: register settings name description address bit setting default decmode demultiplex mode with word clock input enable (1: enabled) 01e 2 1 0
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 74 of 90 figure 5-13: demultiplex mode with 48khz word clock input system example figure 5-14 shows the timing relationship between the audio word clock inputs and word clock outputs when the gs1503b is configured to serial audio output mode. figure 5-14: wcina/b input to wcouta/b output timing diagram muxerrb ch5-8 embedded clock phase information error detect (1: detected) 01e 1C 0 muxerra ch1-4 embedded clock phase information error detect (1: detected) 01e 0C 0 table 5-28: register settings name description address bit setting default aout5/6 gs1503b aout7/8 audio channels 1 & 2 audio channels 3 & 4 audio channels 5 & 6 audio channels 7 & 8 vout[19:0] aout1/2 aout3/4 y/c b /c r [19:0] +3.3v y/c b /c r [19:0] vin[19:0] ain5/6 hd audio embedding module ain7/8 audio channels 1 & 2 audio channels 3 & 4 audio channels 5 & 6 audio channels 7 & 8 ain1/2 ain3/4 48khz (fs) wcina 48khz (fs) wcina mux/demux wcina wcina dec_mode aclka/b wcouta/b 1 clk wcina/b
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 75 of 90 table 5-29: demultiplex mode host interface registers control item name description address bit r/w default video vm_sel video input format (external pin/internal register) configuration select. when set low, the video input format is configured via the vm[3:0] pins. when set high, the video input format is configured via the "vm[3:0]" bits. 000 7 r/w 0 video_det video signal detection flag. set high when 3 consecutive trs are detected in the input video signal. 000 6r 0 crc_err video input signal crc error detection. set high when a crc error is detected in the input video signal. this register is refreshed on every video frame. 000 5r 0 crc_ins video crc insertion. when set high, the luma and chroma line crc words are re-calculated and inserted into the output video signal. 000 4r/w 1 vm[3:0] video input format selection. see table 5-1 . valid when "vm_sel" is high. 000 3-0 r/w 0 ext_sel external exth/extf input select. when set low, the exth and extf pins are configured as outputs. when set high, the gs1503b will insert trs and line numbers based on signals input at the exth and extf pins. 001 3 r/w 0 scrbypass scramble processing bypass select. when set high, the internal scrambler and nrz(i) encoder is bypassed. note: the status of the scrbypass external pin is not updated in this register. the value programmed in this register is logical or'd with the scrbypass external pin setting. 001 2r/w 0 8bit_sel 8-bit input selection. when set high, the gs1503b will accept an 8-bit input video signal. 001 1r/w 0 dscbypass descramble process bypass select. when set high, the internal smpte 292m descrambler is bypassed. note: the status of the dscbypass external pin is not updated in this register. the value programmed in this register is logical or'd with the dscbypass external pin setting. 001 0r/w 0 crc_cnt[11:0] crc error accumulation. reports the accumulated number of crc errors in one video frame. 006 007 3-0 7-0 r0 rsv not used. 008 7-4 r/w 0 vblk_ins vertical blanking enable. when set high, the output video vertical blanking will be set to 040h for the luma channel and 200h for the chroma channel. 008 3 r/w 0
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 76 of 90 hblk_ins horizontal blanking enable. when set high, the output video horizontal blanking, including trs, line numbers and line crc words, will be set to 040h for the luma channel and 200h for the chroma channel. note: if blanking of line numbers and trs words is required, ln_ins and trs_ins must be set low. 008 2 r/w 0 ln_ins line insertion enable. when set high, the gs1503b will insert line numbers into the video data stream. when set low, existing line numbers will remain in the output video stream. 008 1 r/w 1 trs_ins trs insertion enable. when set high, the gs1503b will insert trs codes into the video data stream. when set low, existing trs codes will remain in the output video stream. 008 0 r/w 1 audio am_sel audio input format (external pin/register) configuration select. when set low, the audio input format is configured via the am[1:0] pins. when set high, the audio input format is configured via the "am[1:0]" bits. 010 7 r/w 0 rsv not used. 010 6-2 C 0 am[1:0] audio input format select. see table 5-13 . valid when "am_sel" is high. 010 1-0 r/w 0 rsv not used. 01e 7-3 C 0 decmode demultiplex mode select. when set high, the gs1503b requires a 48khz word clock input at wcina and wcinb. this word clock must be synchronous to the word clock used to embed the audio data. the embedded clock information in the audio data packet will be ignored. see section 5.11 . note: the status of the dec_mode external pin is not updated in this register. the value programmed in this register is logical or'd with the dec_mode external pin setting. 01e 2r/w 0 muxerrb ch5-8 audio sample clock error. when set high, the gs1503b is unable to recover the audio clock phase data in the embedded audio data packet for audio channels 5 to 8. see section 5.11 . 01e 1r 0 muxerra ch1-4 audio sample clock error. when set high, the gs1503b is unable to recover the audio clock phase data in the embedded audio data packet for audio channels 1 to 4. see section 5.11 . 01e 0r 0 table 5-29: demultiplex mode host interface registers (continued) control item name description address bit r/w default
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 77 of 90 audio channel status block audio_cs[7:0] : audio_cs [183:176] audio channel status. when "cs_mode" is set high, the 23 8-bit bytes of the audio channel status block, as defined in aes3-1992, are available in these registers. valid in both aes/ebu and serial audio modes. when "cs_mode" is set low, the audio channel status information in the aes/ebu audio outputs will be replaced with data programmed in these registers. valid only in aes/ebu audio mode. 058 : 06e 7-0 : 7-0 r0 rsv not used 06f 7-6 C 0 cs_wend audio channel status write flag. when set high, indicates that the audio channel status information has been written into the host interface registers 058h to 06eh and can be read by the user. valid only when "cs_mode" is set high. 06f 5 r 0 cs_rqst audio channel status request. when set high, the gs1503b will read and store the audio channel status information from the audio channel set in host interface register "ch_sel[2:0]". valid only when "cs_mode" is set high. 06f 4 r/w 0 cs_mode audio channel status mode. when set high, the user can access the embedded audio channel status information from the host interface registers 058h to 06eh. valid in both aes/ebu and serial audio modes. when set low, the audio channel status information for all audio outputs will be replaced with data programmed in host interface registers 058h - 06eh. valid only in aes/ebu audio mode. 06f 3 r/w 0 ch_sel[2:0] audio channel status select. designates the embedded audio channel from which the audio channel status information will be demultiplexed. the setting 000b represent audio channel 1, through to 111b for channel 8. valid only when "cs_mode" is set high. 06f 2-0 r/w 000b audio data packet adpg4_det audio group 4 data packet detect. when set high, audio data packets with group 4 did have been detected in the incoming chroma video data stream. note: once this bit has been set, it will remain set until a device reset is performed. 013 7 r 0 adpg3_det audio group 3 data packet detect. when set high, audio data packets with group 3 did have been detected in the incoming chroma video data stream. note: once this bit has been set, it will remain set until a device reset is performed. 013 6r 0 table 5-29: demultiplex mode host interface registers (continued) control item name description address bit r/w default
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 78 of 90 adpg2_det audio group 2 data packet detect. when set high, audio data packets with group 2 did have been detected in the incoming chroma video data stream. note: once this bit has been set, it will remain set until a device reset is performed. 013 5r 0 adpg1_det audio group 1 data packet detect. when set high, audio data packets with group 1 did have been detected in the incoming chroma video data stream. note: once this bit has been set, it will remain set until a device reset is performed. 013 4r 0 rsv not used. 013 3-2 C 0 eccb_on ch5-8 error correction enable. when set high, the gs1503b will perform error correction on audio data packets for channels 5 to 8, based on the six ecc words. 013 1r/w 1 ecca_on ch1-4 error correction enable. when set high, the gs1503b will perform error correction on audio data packets for channels 1 to 4, based on the six ecc words. 013 0r/w 1 cascade cascade select. when set high, the gs1503b will default to audio groups 3 and 4. when set low, the gs1503b will default to audio groups 1 and 2. note: the status of the cascade external pin is not updated in this register. the value programmed in this register is logical or'd with the cascade external pin setting. 014 7 r/w 0 rsv not used. 014 6C 0 amuteb ch5-8 audio mute enable. when set high, the multiplexed audio packets for audio channels 5 to 8 are forced to zero. note: the status of the mute external pin is not updated in this register. the value programmed in this register is logical or'd with the mute external pin setting. 014 5r/w 0 amutea ch1-4 audio mute enable. when set high, the multiplexed audio packets for audio channels 1 to 4 are forced to zero. note: the status of the mute external pin is not updated in this register. the value programmed in this register is logical or'd with the mute external pin setting. 014 4r/w 0 table 5-29: demultiplex mode host interface registers (continued) control item name description address bit r/w default
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 79 of 90 dataidb[1:0] ch5-8 audio group did setting. designates the audio group did for audio channels 5 to 8. see table 5-19 . when cascade (external pin or register) is set low, the default setting is audio group 2. when cascade is set high, the default setting is audio group 4. 014 3-2 r/w 10b dataida[1:0] ch1-4 audio group did setting. designates the audio group did for audio channels 1 to 4. see table 5-19 . when cascade (external pin or register) is set low, the default setting is audio group 1. when cascade is set high, the default setting is audio group 3. 014 1-0 r/w 11b dbnb_err ch5-8 audio data packet dbn error. when set high, a data block number error has been detected in the audio data packet for audio channels 5 to 8. 015 7 r 0 adpb8b_err ch5-8 audio data packet 'bit 8' error. when set high, a 'bit 8' error has been detected in the audio data packet for audio channels 5 to 8. 015 6r 0 eccb_err ch5-8 audio data packet error. when set high, an error has been detected in the audio data packet for audio channels 5 to 8, based on the six ecc words. 015 5r 0 adpcsb_err ch5-8 audio data packet cs error. when set high, a checksum error has been detected with the audio data packet for audio channels 5 to 8. 015 4r 0 dbna_err ch1-4 audio data packet dbn error. when set high, a data block number error has been detected in the audio data packet for audio channels 1 to 4. 015 3r 0 adpb8a_err ch1-4 audio data packet 'bit 8' error. when set high, a 'bit 8' error has been detected in the audio data packet for audio channels 1 to 4. 015 2r 0 ecca_err ch1-4 audio data packet error. when set high, an error has been detected in the audio data packet for audio channels 1 to 4, based on the six ecc words. 015 1r 0 adpcsa_err ch1-4 audio data packet cs error. when set high, a checksum error has been detected with the audio data packet for audio channels 1 to 4. 015 0r 0 correctb [11:0] ch5-8 ecc correctable packets. designates the number of audio data packets for channels 5 to 8 that have been corrected in one video frame using the bch forward error correction system. 016 017 3-0 7-0 r0 table 5-29: demultiplex mode host interface registers (continued) control item name description address bit r/w default
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 80 of 90 no_correctb [11:0] ch5-8 ecc un-correctable packets. designates the number of audio data packets for channels 5 to 8 that could not be corrected in one video frame using the bch forward error correction system. 018 019 3-0 7-0 r0 correcta [11:0] ch1-4 ecc correctable packets. designates the number of audio data packets for channels 1 to 4 that have been corrected in one video frame using the bch forward error correction system. 01a 01b 3-0 7-0 r0 no_correcta [11:0] ch1-4 ecc un-correctable packets. designates the number of audio data packets for channels 1 to 4 that could not be corrected in one video frame using the bch forward error correction system. 01c 01d 3-0 7-0 r0 audio control packet acpg4_det audio group 4 control packet detect. when set high, audio control packets with group 4 did h a v e b e e n d e t e c t e d i n t h e i n c o m i n g l u m a v i d e o data stream. 020 7 r 0 acpg3_det audio group 3 control packet detect. when set high, audio control packets with group 3 did h a v e b e e n d e t e c t e d i n t h e i n c o m i n g l u m a v i d e o data stream. 020 6r 0 acpg2_det audio group 2 control packet detect. when set high, audio control packets with group 2 did h a v e b e e n d e t e c t e d i n t h e i n c o m i n g l u m a v i d e o data stream. 020 5r 0 acpg1_det audio group 1 control packet detect. when set high, audio control packets with group 1 did h a v e b e e n d e t e c t e d i n t h e i n c o m i n g l u m a v i d e o data stream. 020 4r 0 rsv not used. 020 3C 0 ctronb ch5-8 audio control packet demultiplex enable. when set high, the audio control packets in the luma channel of the video data stream for audio channels 5 to 8 will be demultiplexed. 020 2r/w 1 ctridb[1:0] ch5-8 audio control packet did setting. designates the audio control packet did for audio channels 5 to 8. see table 5-24 . the default setting is audio group 2. 020 1-0 r/w 10b af_nob[8:0] ch5-8 audio frame number. designates the audio frame number for audio channels 5 to 8. 021 022 0 7-0 r/w 0 rateb[2:0] ch5-8 sampling frequency. designates the audio sampling frequency for audio channels 5 to 8, taken from the rate word of the audio control packet as defined in smpte 299m. 023 3-1 r/w 0 table 5-29: demultiplex mode host interface registers (continued) control item name description address bit r/w default
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 81 of 90 asxb ch5-8 synchronization. when set high, the "asx" bit of the audio control packet rate word designates audio channels 5 to 8 as asynchronous, as per smpte 299m. when set low, the "asx" bit of the audio control packet rate word designates synchronous audio. 023 0r/w 0 del1-2b[25:0] ch5/6 delay data. designates the accumulated audio processing delay relative to video for audio channels 5 and 6. 024 025 026 027 1-0 7-0 7-0 7-0 r/w 0 del3-4b[25:0] ch7/8 delay data. designates the accumulated audio processing delay relative to video for audio channels 7 and 8. 028 029 02a 02b 1-0 7-0 7-0 7-0 r/w 0 rsrvb[17:0] ch5-8 reserve words. designates the value set in the rsrv words of the audio control packet for audio channels 5 to 8, as per smpte 299m. 02c 02d 02e 1-0 7-0 7-0 r/w 0 rsv not used. 02f 7-3 C 0 ctrona ch1-4 audio control packet demultiplex enable. when set high, the audio control packets in the luma channel of the video data stream for audio channels 1 to 4 will be demultiplexed. 02f 2r/w 1 ctrida[1:0] ch1-4 audio control packet did setting. designates the audio control packet did for audio channels 1 to 4. see table 5-24 . the default setting is audio group 1. 02f 1-0 r/w 11b af_noa[8:0] ch1-4 audio frame number. designates the audio frame number for audio channels 1 to 4. 030 031 0 7-0 r/w 0 ratea[2:0] ch1-4 sampling frequency. designates the audio sampling frequency for audio channels 1 to 4, taken from the rate word of the audio control packet as defined in smpte 299m. 032 3-1 r/w 0 asxa ch1-4 synchronization. when set high, the "asx" bit of the audio control packet rate word designates audio channels 1 to 4 as asynchronous, as per smpte 299m. when set low, the "asx" bit of the audio control packet rate word designates synchronous audio. 032 0r/w 0 del1-2a[25:0] ch1/2 delay data. designates the accumulated audio processing delay relative to video for audio channels 1 and 2. 033 034 035 036 1-0 7-0 7-0 7-0 r/w 0 table 5-29: demultiplex mode host interface registers (continued) control item name description address bit r/w default
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 82 of 90 del3-4a[25:0] ch3/4 delay data. designates the accumulated audio processing delay relative to video for audio channels 3 and 4. 037 038 039 03a 1-0 7-0 7-0 7-0 r/w 0 rsrva[17:0] ch1-4 reserve words. designates the value set in the rsrv words of the audio control packet for audio channels 1 to 4, as per smpte 299m. 03b 03c 03d 1-0 7-0 7-0 r/w 0 table 5-29: demultiplex mode host interface registers (continued) control item name description address bit r/w default
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 83 of 90 packet delete rsv not used. 040 7-2 C 0 anci ancillary data delete. when set high, all ancillary data packets ("del_sel" is low) or ancillary data packets with dids designated in host interface registers 041h and 042h ("del_sel" is high) are removed from the video signal. the ancillary data packets are replaced with blanking codes. the data contained in the packets are output at the corresponding pins. when set low, all ancillary data packets remain in the video signal. note: the status of the anci external pin is not updated in this register. the value programmed in this register is logical or'd with the anci external pin setting 040 1 r/w 0 del_sel ancillary data delete mode select. when set high, individual audio groups can be deleted from the video signal by programming host interface register 041h. when set low, all ancillary data packets are deleted from the video signal. 040 0 r/w 0 adpg4_del audio group 4 data packet delete. when set high, all audio data packets with group 4 did will be deleted from the chroma video data stream. valid only when "del_sel" is high. 041 7 r/w 0 adpg3_del audio group 3 data packet delete. when set high, all audio data packets with group 3 did will be deleted from the chroma video data stream. valid only when "del_sel" is high. 041 6 r/w 0 adpg2_del audio group 2 data packet delete. when set high, all audio data packets with group 2 did will be deleted from the chroma video data stream. valid only when "del_sel" is high. 041 5 r/w 0 adpg1_del audio group 1 data packet delete. when set high, all audio data packets with group 1 did will be deleted from the chroma video data stream. valid only when "del_sel" is high. 041 4 r/w 0 acpg4_del audio group 4 control packet delete. when set high, all audio control packets with group 4 did will be deleted from the luma video data stream. valid only when "del_sel" is set high. to be fixed. 041 3 r/w 0 acpg3_del audio group 3 control packet delete. when set high, all audio control packets with group 3 did will be deleted from the luma video data stream. valid only when "del_sel" is high. to be fixed. 041 2 r/w 0 table 5-29: demultiplex mode host interface registers (continued) control item name description address bit r/w default
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 84 of 90 acpg2_del audio group 2 control packet delete. when set high, all audio control packets with group 2 did will be deleted from the luma video data stream. valid only when "del_sel" is high. to be fixed. 041 1 r/w 0 acpg1_del audio group 1 control packet delete. when set high, all audio control packets with group 1 did will be deleted from the luma video data stream. valid only when "del_sel" is high. to be fixed. 041 0 r/w 0 ndid[7:0] arbitrary data packet delete. designates the did for the arbitrary data packets to be deleted from the luma video data stream. valid only when "del_sel" is high. 042 7-0 r/w 0 arbitrary data packet arbiton arbitrary data packet demultiplex. valid only when "arbitmode" is high. when set high, arbitrary data packets will be demultiplexed from the luma video data stream. must be set low again to access valid data in the "arbitudw" registers. 050 1 r/w 0 arbitmode arbitrary packet mode select. when set high, arbitrary data packets are demultiplexed and the user data words are stored in host interface registers 100h to 1feh. no data will be output on the pkt[7:0] external pins and ptkten will be low. when set low, arbitrary data packets are demultiplexed and output at the pkt[7:0] external pins. 050 0 r/w 0 arbitdid[7:0] arbitrary packet data id setting. designates the 8 lsbs of the did word of the arbitrary data packet to be demultiplexed. the 2 msbs are internally generated. "arbitdid[7]" is the msb and "arbitdid[0]" is the lsb. valid only when "arbitmode" is high. 051 7-0 r/w 0 arbitsdid[7:0] arbitrary packet secondary data id setting. designates the 8 lsbs of the secondary did word of the arbitrary data packet to be demultiplexed. the 2 msbs are internally generated. "arbitsdid[7]" is the msb and "arbitsdid[0]" is the lsb. valid only when "arbitmode" is high. 052 7-0 r/w 0 arbitdc[7:0] arbitrary packet dc setting. designates the 8 lsbs of the data count word of the arbitrary data packet to be demultiplexed. the 2 msbs are internally generated. "arbitdc[7]" is the msb and "arbitdc[0]" is the lsb. valid only when "arbitmode" is high. 053 7-0 r/w 0 arbitlineb [11:0] field 2 arbitrary packet demultiplex line number setting. designates the field 2 video line from which the arbitrary data packets will be demultiplexed. valid only when "arbitmode" is high. 054 055 3-0 7-0 r/w 0 table 5-29: demultiplex mode host interface registers (continued) control item name description address bit r/w default
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 85 of 90 arbitlinea [11:0] field 1 arbitrary packet demultiplex line number setting. designates the field 1 video line from which the arbitrary data packets will be demultiplexed. valid only when "arbitmode" is high. 056 057 3-0 7-0 r/w 0 arbitudw0 : arbitudw254 arbitrary packet user data word. designates the 8 lsbs for up to 255 arbitrary packet user data words. arbitrary data can be read from these registers once "arbiton" has been set high to low. valid only when "arbitmode" is high. 100 : 1fe 7-0 : 7-0 r/w 0 table 5-29: demultiplex mode host interface registers (continued) control item name description address bit r/w default
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 86 of 90 6. using the gs1503b with the gs4911b or gs4910b in serial audio multiplex mode, the gs4911b or gs4901b can be used to provide clocks for the input audio. figure 6-1 shows this arrangement. figure 6-1: using the gs1503b with the gs4911b or gs4910b in serial audio mode gs1503b vin[19:0] pclk aclka wcina ain1/2 gs49x1b aclk1 hsync vsync fsync hv f pclk (74.25mhz) video data aclka (128fs) wclka (48khz) ain1/2 ain3/4 aclkb wcinb ain5/6 ain7/8 ain3/4 ain5/6 ain7/8 aclkb (128fs) wclkb (48khz) audio chain aclk2 aclk3 video chain sclk (128fs) mclk (256fs)* wclk (48khz) *optional
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 87 of 90 7. references & bibliography smpte 260m 1999 1125/60 high-definition production system - digital representation and bit-parallel interface smpte 274m 1998 1920 x 1080 scanning and analog and parallel digital interfaces for multiple picture rates smpte 291m 1998 ancillary data packet and space formatting smpte 292m 1998 bit-serial digital interface for high-definition television systems smpte 295m 1997 1920 x 1080 50 hz - scanning and interfaces smpte 296m 2001 1280 x 720 scanning, analog and digital representation and analog interface smpte 299m 1997 24-bit digital audio format for hdtv bit-serial interface smpte rp211 2000 implementation of 24p, 25p and 30p segmented frames for 1920 x 1080 production format aes3-1992 (ansi s4.40-1992) aes recommended practice for digital audio engineering - serial transmission format for two-channel linearly represented digital audio data aes-3id-2001 aes information document for digital audio engineering - transmission of aes3 formatted data by unbalanced coaxial cable ebu tech. 3250-e specification of the digital au dio interface (the aes/ebu interface) (second edition 1992) society of motion picture and television engineers: http://www.smpte.org audio engineering society: http://www.aes.org european broadcast union: http://www.ebu.ch
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 88 of 90 8. packaging & ordering information 8.1 package dimensons 8.2 packaging data 108 73 72 109 144 37 36 1 18.0 ?0.4 18.0 ?0.4 16.0 ?0.1 16.0 ?0.1 1.20 max 1.0 ?0.1 0.4 0.13-0.23 1.0 ref 0.50 ?.2 0? min 8? max dimensions in millimetres 0.1 index a view on a-a 0.09-0.20 144 pin tqfp parameter value package type 144 pin tqfp moisture sensitivity level 3 junction to case thermal resistance, j-c 4c/w junction to air thermal resistance, j-a (at zero airflow) 39c/w pb-free and rohs compliant yes
gs1503b hd embedded audio codec data sheet 37953 - 1 december 2009 89 of 90 8.3 ordering information part number package tem p er a t u re pb-free rohs-compliant GS1503BCVE2 144 pin tqfp 0c to 70c yes yes
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